For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received.

In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

A timing signal diagnostic system includes a chassis housing an input system that receives a timing signal, a timing system that receives the timing signal from the input system, an analog-to-digital converter system that receives the timing signal from the input system, and a processing system that is coupled to the timing system and the analog-to-digital converter system. The processing system uses the timing system to output reference time signals to the analog-to-digital converter system that are based on the timing signal, and uses the analog-to-digital converter system to sample the timing signal based on the reference time signals over a plurality of different timing signal cycles. Based on the sampling of the timing signal, the processing system generates a waveform for the timing signal, and provides a timing signal diagnostic result based on the waveform for the timing signal.