An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously averages out the bandwidth mismatch contribution to the offset.

The subject technology is directed to light detection and ranging (LIDAR) systems and methods. In an embodiment, the subject technology provides a device comprising an optical module configured to receive a first optical signal and a first circuit configured to generate a first electrical signal based on the first optical signal. The device also comprises a first comparator configured to generate a second electrical signal by comparing the first electrical signal to a first threshold value. The device further comprises a first filter configured to generate a first pulse based on the second electrical signal. The first pulse comprises a first point associated with a first timestamp. The timestamp data may be briefly retained in the analog domain, followed by subsequent digital conversion, allowing for significant power savings and reduced system bandwidth. There are other embodiments as well.

Embodiments herein describe a comparator with a preamplifier that includes output transistors that help drive output nodes of a latch. In one embodiment, when the latch is in an active mode, the output transistors in the preamplifier help latch transistors in the latch to drive the output nodes of the latch to a valid (e.g., correct) output. In one embodiment, the output transistors and the latch transistors form parallel current paths to the output nodes, which substantially increase the latch speed.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

The present disclosure relates to an analog-to-digital converter, comprising: one or more comparators, each signal with a variable configured to compare an analog reference level specific to the comparator; a controller coupled to an output of the one or more comparators and configured to generate a control signal indicating the reference level of each comparator as a function of an output signal from each of the one or more comparators and configured to generate a digital output signal based on the output signal from each of the one or more comparators.

A neuromorphic computing device includes a first memory cell array comprising a plurality of resistive memory cells and configured to output a plurality of read currents through a plurality of bit lines or source lines; a second memory cell array comprising a plurality of reference resistive memory cells and configured to output at least one reference current through at least one reference bit line or at least one reference source line; a current-to-voltage converting circuit configured to output a plurality of signal voltages respectively corresponding to the plurality of read currents and output at least one reference voltage corresponding to the at least one reference current; and an analog-to-digital converting circuit configured to convert the plurality of signal voltages to a plurality of digital signals using the at least one reference voltage and output the plurality of digital signals.

A FLASH-SAR ADC conversion method comprises: at a sampling stage of a FLASH-SAR ADC, sampling an input signal by a SAR ADC module, and at the same time, performing amplification, comparison and high-bit coarse quantization on the input signal by a FLASH ADC module to output a FLASH ADC conversion result, wherein the FLASH ADC conversion result is a temperature code; at a conversion stage of the FLASH-SAR ADC, performing fine quantization on a residual voltage by the SAR ADC module according to the temperature code and the input signal to output a SAR ADC conversion result, and at the same time, sampling a reference voltage or a partial voltage of the reference voltage by FLASH ADC module; and performing encoding on the temperature code and the SAR ADC conversion result to obtain a signal conversion result of the FLASH-SAR ADC.

An ADC receives a first input signal and a second input signal and outputs a digital signal. The first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference. The ADC includes a voltage conversion circuit and multiple comparators. The voltage conversion circuit generates an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage. The comparators compare the intermediate voltage with N times a reference voltage, where N is greater than or equal to negative one and less than or equal to one. The intermediate voltage is the common-mode voltage plus or minus M times the voltage difference, where M is two to the power of R, and R is a positive integer.