A system and method for detection of an event and recording data associated with the event. An application-specific integrated circuit (ASIC) for event-driven data acquisition from detector is disclosed. The event-driven circuitry stays silent when there is no event detected on the detector. The event-driven data acquisition system consumes small power and may consume no memory during waiting for an event. Once the event arrives (e.g. photons, particle or ion hits the detector panel), the event is detected and recorded. The ASIC includes multi-channel ADCs (or ADC arrays) with flexible resolution which enables an option to operate at a lower resolution during the silent period to save power.

The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

A method is described that is performed by a calibration system. The method includes determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system; generating a set of digital test values for determining the accuracy of the analog-to-digital converter; and applying the set of perturbation values to the set of digital test values to generate a set of modified test values, wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain.

Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.

Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.

Disclosed herein are some examples of algorithmic analog-to-digital converters (AADCs) that perform noise shaping. In particular, an AADC disclosed herein includes circuitry that can store residue(s) of one or more conversion cycles produced by the AADC and apply a value corresponding to the residue(s) to a subsequent conversion cycle. The AADC may perform a filtering procedure with the residue(s) to produce the value applied to the subsequent conversion. Applying the value to the subsequent conversion cycle can increase a signal-to-noise ratio of the signal that the AADC is converting in the subsequent conversion cycle.

Disclosed herein are some examples of algorithmic analog-to-digital converters (AADCs) that perform noise shaping. In particular, an AADC disclosed herein includes circuitry that can store residue(s) of one or more conversion cycles produced by the AADC and apply a value corresponding to the residue(s) to a subsequent conversion cycle. The AADC may perform a filtering procedure with the residue(s) to produce the value applied to the subsequent conversion. Applying the value to the subsequent conversion cycle can increase a signal-to-noise ratio of the signal that the AADC is converting in the subsequent conversion cycle.

An image sensing system and methods for operating the same are disclosed. An image sensing system includes a plurality of pixel circuits, a multiplexer configured to select one of the pixel circuit and provide analog pixel data without sampling, and a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the analog pixel data into digital data. The SAR ADC includes a capacitive digital-to-analog converter (CDAC) configured to convert contents of the SAR into a corresponding analog signal for comparison, by a comparator, with the analog pixel data. The CDAC includes a two-dimensional array of circuit elements. A control circuit in the image sensing system is configured to cause random ones of the circuit elements of the CDAC to be selected for generation of the corresponding analog signal and add a dithering signal so a CDAC output and shuffle a multiplexer switch sequence to improve fixed pattern noise.

Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.

Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.