The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.