An analog-to-digital converter (ADC) having an input operable to receive an input voltage, V.sub.IN, and an output operable to output a digital code representative of V.sub.IN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

A dynamic comparator includes a differential amplifier stage, a switching unit and a switching charge storage unit. The switching charge storage unit includes a plurality of switching transistors, and a charge storage capacitor electrically connected to the plurality of switching transistors. When an operational mode of the dynamic comparator is switched from a comparison state to a reset state, a voltage on one of a first terminal and a second terminal of the charge storage capacitor is increased from a half of the system voltage to a system voltage, so as to implement a charge recycle effect. The dynamic comparator of the present invention can have lower power consumption and lower charge-discharge current.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.