This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (S.sub.IN) at an input node (102) and outputs a corresponding time-encoded signal (S.sub.OUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (S.sub.IN) to the feedback signal (S.sub.FB) with hysteresis. This provides a pulse-width modulated output signal (S.sub.OUT) where the duty cycle encodes the input signal (S.sub.IN).

An electrical circuit can bias a sensor, measure current from a sensor, or both of these. In some examples, the electrical circuit can include a comparator having two input terminals and an output terminal. The comparator can be configured to compare input signals applied to the two input terminals and generate an output signal at the output terminal based on the comparison. The electrical circuit can include a switch having a control terminal that is electrically coupled to the output terminal of the comparator. The switch can also include a first connection terminal that is electrically coupled to the sensor and a second connection terminal that is electrically coupled to a charge-packet source. The switch can be switchable between (i) an open state to electrically decouple the sensor from the charge-packet source, and (ii) a closed state to electrically couple the sensor to the charge-packet source.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CT achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

A system may include a voltage regulator controller and a driver. The voltage regulator controller may be configured to maintain a phase voltage. The driver may be associated with the phase voltage. The driver may include a first signal line that may be communicatively coupled to the voltage regulator controller. The driver may be configured to transmit a multiplexed signal on the first signal line to the voltage regulator controller.

A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

A system may include a voltage regulator controller and a driver. The voltage regulator controller may be configured to maintain a phase voltage. The driver may be associated with the phase voltage. The driver may include a first signal line that may be communicatively coupled to the voltage regulator controller. The driver may be configured to transmit a multiplexed signal on the first signal line to the voltage regulator controller.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CT achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.