The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage.

The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (I.sub.D1, I.sub.D2, . . . I.sub.Dj) based on a respective input data value (D.sub.1, D.sub.2, . . . D.sub.j). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

An apparatus and method are disclosed with some embodiments including an analog and time to digital converter (ATDC) including a receiver, the receiver for receiving an analog channel input for conversion to a digital data, the digital data having at least one bit, and a defined absolute reference time stamp, the defined absolute reference time stamp representing an absolute reference time associated with conversion of the analog channel input to the digital data and an analog-to-digital converter, the converter converting the analog channel input to the digital data.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer, a delta-sigma analog-to-digital converter (ADC), a dynamic element matching (DELM) entity configured to compensate for nonlinearity resulting from variation among digital-to-analog conversion (DAC) elements of the ADC, and a control circuit configured to enable and disable the DELM based on a magnitude of a digital signal generated by the ADC.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.