A communication system where a central node (base-station or access point) communicates with multiple clients in its neighbourhood using transparent immediate beam-forming. Resource allocation and channel access is such that the central node does not necessarily know when each client starts its transmission. Receive beam-forming in such a system is not possible, as beam-forming coefficients for each client should be selected according to the particular channel realization from that client to the central node. Each client is detected early in its transmission cycle, based on either a signature that is part of the physical characteristics unique to that client, or based on a signature that is intentionally inserted in the clients' signal, and accordingly adjusts its beam-forming coefficients.

Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.

A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2.sup.N1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.