A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer and a delta-sigma analog-to-digital converter (ADC) with digital-to-analog converter (DAC) element mismatch shaping and more particularly to sensor assemblies and electrical circuits therefor including a dynamic element matching (DELM) entity configured to select DAC elements based on data weighted averaging (DWA) and a randomized non-negative shift.

Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Current steering digital-to-analog converters (DACs) are described. These DACs are suitable for high speed operation. Weight transistors conventionally used in DACs are replaced with resistors, resulting in a lower RC constant. Further, the resistors cause a smaller voltage drop, thus improving the voltage headroom of the DAC. Additionally, the current steering switches are biased in the triode region, as opposed to the saturation region as in conventional designs. Biasing the switches in the triode region results in a smaller drain-source voltage, which further improves the voltage headroom of the DAC. The triode operation further results in a substantially smaller output impedance, which leads to the output voltage being dictated primarily by the output transistor of the current path. Lastly, reset switches are added which reduce data-dependent memory effects that can otherwise produce distortion.

A digital-to-analog converter, including an input to receive a digital signal; a first comparator configured to receive the digital signal and output a first signal based on the digital signal and a first threshold; a second comparator configured to receive the digital signal and output a second signal based on the digital signal and a second threshold, the second threshold different from the first threshold; and an integrator configured to receive the first signal and the second signal and integrate the first signal and the second signal into an analog signal that represents the digital signal.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.

A digital power amplifier comprises: an integrated circuit (IC2); an adaption circuit of discrete components connected to first and second transmission output pins of an integrated circuit to adapt the output signal and feed a substantial sinusoidal output current with a transmission resonance frequency to an RFID antenna. IC2 comprises a digital control section with N wave-forming contacts to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; N driver blocks each connected with a first contact to one of the wave-forming contacts and N/2 of them connected with a second contact to the first transmission output pin and the other N/2 of them connected with their second contact to the second transmission output pin. The driver blocks provide increments of the substantial sinusoidal output current to the first and second transmission output pins.