Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.

A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the n.sup.th current source set is twice a total quantity of current sources of the (n−1).sup.th current source set.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of current-steering cells, each having a bypass switch, and a resistor ladder circuit having multiple segments. Each segment may include a first resistive element and a second resistive element, the bypass switch being configured to selectively provide a bypass current to a common node between the first resistive element and the second resistive element.