A circuit includes a first integration stage, a quantizer, a second integration stage coupled between the first integration stage and the quantizer, and a digital-to-analog converter (DAC). The first integration stage includes a first input node pair configured to receive a pair of differential analog input signals, and the quantizer is configured to generate a digital signal based on the pair of differential analog input signals and a clock signal. The second integration stage includes a second input node pair, and the DAC is configured to receive the digital signal and output feedback signals to at least one input node pair of the first input node pair or the second input node pair.

A current digital to analog converter (DAC) including an offset array including a plurality of unit cells of a first size, and a trimming array including a plurality of unit cells having the first size and a plurality of half cells, wherein the half cells have a larger size than the plurality of unit cells.

A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

A digital-to-analog converter (DAC) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (BBGEN). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (BBGEN) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

A digital-to-analog converter (DAC) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (BBGEN). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (BBGEN) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage.

A D/A converter for converting a digital signal with a predetermined number of bits to an analog signal, the D/A converter includes a plurality of component groups that include a plurality of components included in the D/A converter and are connected to an output unit for outputting the analog signal in a predetermined order; and a start position change unit that changes a start position within the plurality of the component groups used for generating a single analog signal by using a predefined shift pattern when generating the single analog signal corresponding to the digital signal.

A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.