Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.

A display driver includes a D/A converter circuit for outputting a gradation voltage, and an amplifier circuit that is input with a gradation voltage at an input node. The amplifier circuit includes an operational amplifier, resistance provided between the input node and a node, resistance provided between a node and an output node of the operational amplifier, and an adjustment resistance circuit. The adjustment resistance circuit adjusts a first adjustment resistance value, that is a resistance value between a node and an inverting input node of the operational amplifier, and a second adjustment resistance value, that is a resistance value between the node and the inverting input node.

A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

An integrated circuit including a first passive component of capacitive, resistive, or inductive type, including: a plurality of second and third passive components of said type, each having a same first theoretical value Compu_t, the second components being connected together so that their values add, and each third component being associated with a first switch having its state determining whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components of said type, each associated with a second switch having its state determining whether the value of the fourth component adds to the values of the second components, at least one of the fourth passive components having a second theoretical value equal to (1P).Compu_t or to (1+P).Compu_t, P being positive and smaller than .

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data.

A voltage mode signal transmitter includes a front-end signal processor and a signal transformer. The front-end signal processor receives a first and second data signal, and delays and inverts the data signals to generate a third and fourth data signal. The front-end signal processor selects two of the first data signal to the fourth data signal to generate a plurality of signal pairs according to a first control signal. The signal transformer selects one data signal of each of the signal pairs to generate input voltages according to a second control signal, and generates an output voltage according to the input voltages. A working frequency of the first control signal is lower than a working frequency of the second control signal.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.