A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2.sup.n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2.sup.n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the control signal bootstrap circuit (103) and the intermediate level resistor string, where on/off of the first switch group (106) is controlled by the control signal after the bootstrap processing, so as to connect the intermediate level resistor string to the circuit or disconnect the intermediate level resistor string from the circuit.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

An X-ray detector includes an N-channel digital-analogue converter controllable with K+L bits. In an embodiment, the digital-analogue converter includes a first voltage source to provide a plurality of first voltage values at tapping points; and a switch unit with N switch matrices, 2.sup.K inputs of the switch matrices being electrically conductively connected to 2.sup.K tapping points of the first voltage source. The digital-analogue converter also includes a second voltage source including N subunits. The X-ray detector further includes a discriminator unit including N comparators, at least one input of the comparators being electrically conductively connected to the associated output of the switch matrix and/or to the associated output of the subunit, so that the associated first voltage value and the associated second voltage value are associable with each comparator. A signal of an output of a pre-amplifier, and the associated first and second voltage values are comparable in the comparator.

In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.