An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/f.sub.s. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of f.sub.s/R, and drives an analog output responsive to each second digital input for a duration of RT. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of f.sub.s.

An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

A frequency synthesizer includes: a time-to-digital converter configured to output a time-to-digital value corresponding to a time event of a trigger signal with respect to an operating clock signal; a comparison unit configured to compare a value based on the time-to-digital value with a target value; an oscillation unit configured to generate the synthesizer signal; and a frequency adjustment unit configured to adjust a frequency of the synthesizer signal based on a comparison result of the comparison unit. The time-to-digital converter includes: a state transition unit configured to start a state transition in which an internal state transitions based on the time event of the trigger signal and output state information indicating the internal state; a transition state acquisition unit configured to acquire and hold the state information in synchronization with the operating clock signal; and a calculation unit configured to calculate the time-to-digital value according to the number of transition times of the internal state based on the state information acquired by the transition state acquisition unit.

A converter system is disclosed. The converter system including a system controller; a plurality of circuit elements configured to operate in response to control signals from the system controller; a bus controller configured to transmit data to a communication bus; and a plurality of power converters, each including a digital to analog converter (DAC) configured to generate an analog voltage for one or more of the circuit elements based on a digital signal on the communication bus; a digital module configured to receive digital data from the bus controller on the communication bus; and an amplifier, configured to adjust an offset according to an offset compensation code received from the digital module.

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

A converter system is disclosed. The converter system including a system controller; a plurality of circuit elements configured to operate in response to control signals from the system controller; a bus controller configured to transmit data to a communication bus; and a plurality of power converters, each including a digital to analog converter (DAC) configured to generate an analog voltage for one or more of the circuit elements based on a digital signal on the communication bus; a digital module configured to receive digital data from the bus controller on the communication bus; and an amplifier, configured to adjust an offset according to an offset compensation code received from the digital module.

A system and method for calibrating a digital-to-analog converter (DAC) device. The method includes tuning a second subset of one or more DAC segments to match a strength of a first subset of DAC segments wherein the first subset of DAC segments is of a strength nominally equal to that of the second subset of DAC segments. The process is iterative, and the second subset of DAC segments is associated with lesser significant bits than the bits associated with the first subset of DAC segments. The process is repeated to tune each of successive second subsets of DAC segments to corresponding successive first subsets of DAC segments in top-down order from a segment associated with a MSB input to a segment associated with a LSB input. In each case the first subset of DAC segments is of a strength nominally equal to that of the second subset of DAC segments.