A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.

An analog-to-digital converter includes an integrator, a single comparator, a successive approximation result register, and correction circuitry. The comparator is coupled to an output of the integrator. The successive approximation result register is coupled to an output of the comparator. The correction circuitry is configured to determine whether a sum of a reference voltage and an output voltage of the integrator changes an output of the comparator. The correction circuitry is also configured to, responsive to the sum of the reference voltage and the output of the integrator not changing the output of the comparator, add twice the reference voltage to the output of the integrator to produce a bit value at the output of the comparator, and select a bit value to be loaded into the successive approximation result register based on the bit value at the output of the comparator.

Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

A method may include generating, via a sigma-delta DAC, a series of analog voltage levels that are equally spaced across a selected portion of ADC range; measuring, via the ADC, the series of analog voltages levels generated via the sigma-delta DAC; determining an error of a system at least partially based on a comparison of ADC output values and expected ADC output values, the system including the sigma-delta DAC and the ADC; modeling the error of the system using a combination of piecewise linear basis functions representing different types of errors or offsets; and determining a gain error of the ADC at least partially based on a coefficient of a linear basis function corresponding to the gain error of the ADC, the linear basis function one of the piecewise linear basis functions used to model the error of the system.