Proposed is a technology related to a compensation method for excess loop delay (ELD) using a time division switching (TDS) technique. A delta-sigma modulator (DSM) to which the compensation method for excess loop delay is applied includes a single op-amp resonator (SOR) loop filter. The loop filter includes an operational amplifier, a plurality of capacitors connected to each other in series between an input terminal and an output terminal of the operational amplifier, and a plurality of resistor units connected in common to one among nodes between the plurality of capacitors. For at least two of the plurality of resistor units, a resistance value of each of the at least two resistor units is changed according to a clock signal, and a coefficient of a third-order transfer function of the loop filter is changed according to the clock signal, thereby effectively compensating for excess loop delay of the delta-sigma modulator.

A delta-sigma modulation apparatus divides an input signal into a plurality of signal blocks, inputs the plurality of signal blocks to a plurality of delta-sigma modulation circuits, and performs combining processing for combining a plurality of output signals from the plurality of delta-sigma modulation circuits.

A measuring circuit measures an interleaving (IL) spur of at least one time-interleaved digital-to-analog converter (DAC) included in a delta-sigma (DS) analog-to-digital converter (ADC). The measuring circuit includes a dither tone generator circuit and a digital signal processing circuit. The dither tone generator circuit generates a dither tone with a pre-defined tone frequency, and injects the dither tone to the DS ADC. The digital signal processing circuit processes a digital output of the DS ADC with the dither tone injected, to generate a measurement result of the IL spur that is induced by the at least one time-interleaved DAC due to the injected dither tone.

In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Proposed is a technology related to a compensation method for excess loop delay (ELD) using a time division switching (TDS) technique. A delta-sigma modulator (DSM) to which the compensation method for excess loop delay is applied includes a single op-amp resonator (SOR) loop filter. The loop filter includes an operational amplifier, a plurality of capacitors connected to each other in series between an input terminal and an output terminal of the operational amplifier, and a plurality of resistor units connected in common to one among nodes between the plurality of capacitors. For at least two of the plurality of resistor units, a resistance value of each of the at least two resistor units is changed according to a clock signal, and a coefficient of a third-order transfer function of the loop filter is changed according to the clock signal, thereby effectively compensating for excess loop delay of the delta-sigma modulator.

A charge analog-to-digital converter (ADC) for processing a signal from a micro electrical mechanical sensor (MEMS) sensor can include a pre-amplifier integrated into a feedback loop of a delta sigma modulator to provide a reduced power consumption configuration for processing of the signal from the MEMS sensor.

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.