Methods and devices to mitigate time varying impairments in sensors are described. The application of such methods and devices to pressure sensors facing time varying parasitic capacitances due to water droplets is detailed. Benefits of auto-zeroing technique as adopted in disclosed devices is also described.

This analog-to-digital converting device comprises: an input terminal for receiving the analog input signal; an output terminal for issuing the digital output signal; a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected to the input terminal; a first feedback module associated to the first SAR ADC module; a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected in a cascaded manner to the first SAR ADC module; a second feedback module associated to the second SAR ADC module; and a multiplexing module connected to the first and second SAR ADC modules, to deliver the digital output signal.

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

In an embodiment a method includes providing an analog signal comprising a first value of a temperature of an object, performing an analog-to-digital conversion of the analog signal using a first analog-to-digital converter (ADC) thereby providing a first digital signal representing an initial digital temperature value, performing an analog-to-digital conversion of the analog signal using a second ADC thereby providing a second digital signal representing a digital reference temperature value, regularly providing the analog signal comprising a successive value of the temperature of the object, performing the analog-to-digital conversion of the analog signal using the second ADC thereby providing the second digital signal representing a successive digital temperature value, calculating a digital delta temperature value according to a difference between the successive digital temperature value and the digital reference temperature value and repeating providing the analog signal, performing the analog-to-digital conversion and calculating the digital delta temperature value as long as the digital delta temperature value lies within a predefined range.

This analog-to-digital converting device comprises: an input terminal for receiving the analog input signal; an output terminal for issuing the digital output signal; a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected to the input terminal; a first feedback module associated to the first SAR ADC module; a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected in a cascaded manner to the first SAR ADC module; a second feedback module associated to the second SAR ADC module; and a multiplexing module connected to the first and second SAR ADC modules, to deliver the digital output signal.

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.

An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.