An analog-to-digital conversion system includes two quantizers having a least significant bit arranged in a parallel pair. An input circuit coupled to the quantizers provides an analog input signal to the quantizers. A dither generator coupled to the quantizers provides an analog differential dither signal for perturbing quantization of the analog input signal. A combiner coupled to the quantizers adds respective outputs of the quantizers to obtain a linearized digital representation of the analog input signal.

An analog-to-digital conversion system includes two quantizers having a least significant bit arranged in a parallel pair. An input circuit coupled to the quantizers provides an analog input signal to the quantizers. A dither generator coupled to the quantizers provides an analog differential dither signal for perturbing quantization of the analog input signal. A combiner coupled to the quantizers adds respective outputs of the quantizers to obtain a linearized digital representation of the analog input signal.

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.

A sigma-delta modulator includes a plurality of quantizers, an input path, a feedback path, a loop filter, a pre-filter, and a connection path. The plurality of quantizers are configured to produce a plurality of quantized signals. The input path is configured to lead an input signal to the plurality of quantizers. The feedback path is configured to feed back a feedback signal into the input path, and the feedback signal is produced by averaging the plurality of quantized signals. The loop filter is put on the input path before the plurality of quantizers, and the loop filter is configured to receive the input signal and the feedback signal. The pre-filter is configured to output a signal to a corresponding quantizer which is one of the plurality of quantizers.

A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths.