A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A photonic monobit analog-to-digital converter (ADC) includes an incoherent optical source configured to generate an optical noise signal, an optical modulator, at least one coupler, a photodetector, a limiter, and a DSP. The optical modulator is configured to modulate an input optical signal using an analog input electrical signal to generate an optical modulated signal. The coupler is configured to couple the optical modulated signal with the optical noise signal to generate at least one coupled signal. The photodetector is configured to generate a phase difference between the optical modulated signal and the optical noise signal using the at least one coupled signal. The limiter is configured to generate a decision signal based on the phase difference, and the DSP is configured to output a digital signal representative of the analog input electrical signal based on the decision signal.

A distributive photonic monobit analog-to-digital converter includes a plurality of signal processing chains configured to receive a corresponding plurality of analog input electrical signals. Each processing chain includes an incoherent optical source configured to generate an optical noise signal, an optical modulator configured to modulate an analog input electrical signal of the plurality of analog input electrical signals onto an input optical signal to generate an optical modulated signal, a coupler configured to couple the optical modulated signal with the optical noise signal to generate a coupled signal, a photodetector configured to generate a phase difference between the optical modulated signal and the optical noise signal using the coupled signal, and a limiter configured to output a decision signal based on the phase difference and using a clock signal. A multi-phase clock generator is configured to generate the clock signal for each of the plurality of signal processing chains.

Disclosed is a digital stereo multiplexing-demultiplexing system based on the use of delta-sigma modulation. Creation of left (LR) and right (L+R) channels is achieved using a binary delta adder IC circuit. Delta adder is an ordinary binary adder with an interchanged role of the Sum and Carry-Out terminals. Two channel multiplexer and demultiplexer are implemented with ordinary binary logic gates. Output of the multiplexer is modulated and transmitted to the receiver where demultiplexing is performed. The proposed method can combine two or more digital stereo channels. This method is not application limited, and can be used in acoustic, video, or photo applications.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A signal receiver includes a multiplexer, a sub-sample analog-to-digital converter (ADC) and a received signal strength indicator (RSSI) estimator for a signal receiver with multiple stage cascade amplifiers architecture. The multiplexer may select one of the input signal of each stage of cascade amplifiers or the last stage output signal of cascade amplifiers as a selected signal according to a selection signal. The sub-sample ADC may perform a sub-sampling operation using the selected signal to generate sampled data. The RSSI estimator may calculate a RSSI value corresponding to the selected signal according to the sampled data.

An apparatus for a signal processor for Wide-Band Applications is provided. The signal processor includes a plurality of parallel branches. Each parallel branch includes a frequency shifter, a sigma-delta-modulator, and a filter. The output signal of each branch is combined via a signal recombiner. The signal processor is suitable for wide-band applications due to centering the zeros of the sigma-delta-modulator's noise transfer function and filter's noise transfer function at the frequency of the frequency shifter in the same branch of the signal processor. Centering these zeros at the frequency of the frequency shifter shapes the quantization noise added by the sigma-delta-modulator away from the input signal frequency to make it easier to remove the quantization noise. This wideband performance is also achieved due to the design of the embodiment's filters. The embodiments of this invention use filters with symmetric transition bands and a pass-band that is wide enough for use in wireless applications.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered. A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.