The present disclosure discloses a touch sensing signal processing circuit which senses a change in capacitance of a sensing node for touch sensing and provides a logic signal corresponding to the touch sensing. The touch sensing signal processing circuit of the present disclosure is configured using a delta-sigma analog to digital converter. Auto-tuning may be performed by delta-sigma analog conversion.

A delta-sigma modulation type A/D converter includes: a capacitively coupled amplifier having a sampling capacitor, a feedback capacitor, and an amplifier; a correlated double sampling type first integrator as a first-stage integrator, which is connected to the capacitively coupled amplifier without a switch; a second integrator arranged after the first integrator; a quantizer arranged after the second integrator and quantizing an output of the second integrator; and an D/A converter that D/A-converts an output of the quantizer and feeds back to any one of the capacitively coupled amplifier, the first integrator, and the second integrator.

A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

A delta-sigma modulator is provided with: a loop filter 30; a quantizer 36 that generates quantized data on the basis of an output from the loop filter 30; an internal path 42 connected to the loop filter 30 or the quantizer 36; and a compensator 38 that provides, to the internal path 42, a compensation signal for compensating for distortion that occurs in a frequency component at a target frequency, the frequency component being among frequency components of a pulse train corresponding to the quantized data.

A photoelectric conversion device comprising a pixel unit in which a plurality of pixels each comprising a photoelectric conversion element are arranged in a matrix, and a plurality of delta-sigma AD converters each configured to convert a signal output from the pixel unit into a digital signal, is provided. The plurality of delta-sigma AD converters are divided into at least two groups having different timings of starting AD conversion from each other when converting, into digital signals, signals output from the pixels selected out of the plurality of pixels via a common pixel control line.

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.

An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.