At least one embodiment relates to generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF signal is modulated based on the digital baseband signal. Pulses of the pulse sequence are quantized based on a time grid of a third clock rate. A ratio between a number of second clock cycles corresponding to one first clock cycle and a number of third clock cycles corresponding to one first clock cycle is non-integer.

A signal processing apparatus is provided which can suppress external noise without degrading an audio characteristic.

Provided is a signal processing apparatus including: an A/D converter configured to output a digital signal having a predetermined sampling frequency and quantization bit number a, the A/D converter including a first delta sigma modulator that performs a first delta sigma modulation process on an input analog signal; a filter unit configured to pass an output of the A/D converter through a digital filter provided with a predetermined filter characteristic and output a digital signal having the sampling frequency and a quantization bit number b; a second delta sigma modulator configured to perform a second delta sigma modulation process on an output of the filter unit and output a digital signal having the sampling frequency and the quantization bit number a; and an addition unit configured to add an output of the second delta sigma modulator and an input digital signal having the sampling frequency and the quantization bit number.

Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.

A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

At least one embodiment relates to generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF signal is modulated based on the digital baseband signal. Pulses of the pulse sequence are quantized based on a time grid of a third clock rate. A ratio between a number of second clock cycles corresponding to one first clock cycle and a number of third clock cycles corresponding to one first clock cycle is non-integer.

An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analog-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analog-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal. The comparator comprises a comparator-input-terminal configured to receive the loop-integrator-output-signal; a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

Certain aspects of the present disclosure provide apparatus and techniques for segmenting a digital input signal for digital-to-analog conversion. For example, certain aspects provide a segmentation circuit for generating digital signal segments for a digital-to-analog converter. The segmentation circuit generally includes a modulo function logic circuit configured to generate a modulo output signal based on a digital input signal and a divisor input signal and a modulo range extension logic circuit configured to selectively direct the modulo output signal or the divisor input signal to an output of the segmentation circuit. In certain aspects, the output of the segmentation circuit may be used by the digital-to-analog converter to generate an analog signal based on the digital input signal.

A digital-to-analog converter performs a computation process to start the computation based upon the second clock signal with respect to the digital data of music sound if the computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the computation based upon the second clock signal from being started with respect to the digital data of music sound until the computation is not under execution when the computation is under execution, and an output process to convert a computation result of the computation process into an analog signal and output the analog signal.

A digital-to-analog converter performs a computation process to start the computation based upon the second clock signal with respect to the digital data of music sound if the computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the computation based upon the second clock signal from being started with respect to the digital data of music sound until the computation is not under execution when the computation is under execution, and an output process to convert a computation result of the computation process into an analog signal and output the analog signal.