The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.

An access point (AP) that supports the IEEE 802.11ba protocol may transmit a frame including a physical layer (PHY) preamble to one or more stations (STAs) over a channel. The PHY preamble may include a plurality of repeated modulated legacy signal (L-SIG) fields to spoof a recipient of the frame and protect a wake up signal (WUS) to be subsequently transmitted by the AP. The AP may transmit the WUS to at least a first STA of the one or more STAs, wherein the at least the first STA is a IEEE 802.11ba compliant STA.

Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.

The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.

A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.