A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.

In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.

A method of transition encoding including: receiving a data packet having a packet size; identifying one or more forbidden patterns in the data packet; segmenting the data packet into a plurality of segments based on a location of the one or more forbidden patterns in the data packet; and encoding the plurality of segments by removing the one or more forbidden patterns, and appending position indicator bits according to positions of the segments in the data packet.

The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity.

There are provided: a calculation section dividing inputted data into N bits to calculate a first running disparity of a data string of the N bits; a determination section determining whether the data string of the N bits is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated at a time point before the first running disparity; and an addition section inverting or non-inverting the data string of the N bits based on a result of the determination by the determination section to add a flag indicating the result of the determination by the determination section for outputting. The technology is applicable to a device communicating in an SLVS-EC specification.

The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.