An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.

The present invention relates to an encoding apparatus for multi-level signaling, the encoding apparatus including: a candidate pattern generator (1) generating a set of candidate patterns from input data by using symbol-based inversion; a controller (2) generating a cumulated disparity value that is a result of calculating disparity indicating a degree to which transmission data up to previous transmission deviates from DC balance, storing the cumulated disparity value, and determining a transmission control code by using the cumulated disparity value and a set of disparity values that is a result of calculating disparity indicating a degree to which each of the candidate patterns deviates from DC balance; and a data selector (3) selecting one candidate pattern from the set of the candidate patterns as data to be transmitted, according to the determined transmission control code.

In certain aspects, a method for sending data over a bus comprises: calculating a parity check code for a new data code, wherein the new data code comprises a number of bits in the new data code; calculating a Hamming distance between the new data code and a prior data code; and if the Hamming distance is greater than half of the number of bits in the new data code: inverting the new data code and the parity check code to obtain an inverted new data code and an inverted parity check code; and sending the inverted new data code and the inverted parity check code to the bus.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

In certain aspects, a method for sending data over a bus comprises: calculating a parity check code for a new data code, wherein the new data code comprises a number of bits in the new data code; calculating a Hamming distance between the new data code and a prior data code; and if the Hamming distance is greater than half of the number of bits in the new data code: inverting the new data code and the parity check code to obtain an inverted new data code and an inverted parity check code; and sending the inverted new data code and the inverted parity check code to the bus.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.

Embodiments of this application provide a data transmission method, a communications device, and a storage medium, to reduce pressure caused by a quantity of cross connections between intermediate nodes to the intermediate nodes in a network. In an embodiment of this application, a first communications device obtains Q first code block streams, and obtains a to-be-sent second code block stream based on the Q first code block streams. Q downlink ports are in a one-to-one correspondence with the Q first code block streams, the Q downlink ports correspond to S code block groups, one code block in the Q first code block streams corresponds to one code block group, and the second code block stream obtained by the first communications device includes L code block sets; and for each of the L code block sets, the code block set includes K code blocks corresponding to each of the S code block groups. In the solutions provided in this embodiment of this application, code block streams are multiplexed at a code block granularity, so that a quantity of cross connections between intermediate nodes in a network can be reduced, thereby reducing pressure on network management and operation and maintenance.

In example implementations, an apparatus is provided. The apparatus comprises a processor and a non-transitory computer readable storage medium encoded with instructions executable by a processor, the non-transitory computer-readable storage medium. The non-transitory computer readable storage medium includes instructions to receive a plurality of data having N bits, wherein each of the N bits is binary, select a set of code words for each one of the plurality of data, wherein the code words have M bits, wherein each of the M bits is binary having an approximately equal number of ones and zeros, wherein a value of M is greater than N, and print a reflection and inversion invariant code based on the set of code words to represent data of the plurality of data.

A single-ended inter-chip data transmission system and a single-ended inter-chip data reception system are provided for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus.