Patent classifications
H03M7/3015
AMPLIFIERS WITH DELTA-SIGMA MODULATORS USING PULSE-DENSITY MODULATIONS AND RELATED PROCESSES
An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.
Delta-sigma modulator and modulation method, transmission device, and transmission method
The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.
Huffman packing for delta compression
Huffman packing for delta compression is described. In accordance with the described techniques, delta values between neighboring elements of a data block are generated using delta compression. The delta values are transformed according to a transformation algorithm. The transformed delta values are packed using Huffman encoding to generate compressed data that corresponds to the data block.
SIGNAL AMPLIFICATION AND TRANSMISSION BASED ON COMPLEX DELTA SIGMA MODULATOR
Apparatuses and methods for power amplification and signal transmission using complex delta-sigma modulation are disclosed. In one embodiment, a complex delta sigma modulator unit comprising a complex polar quantizer within an integrator loop is disclosed. The complex polar quantizer quantizes the envelope of a complex integrated signal and produces a complex quantized output signal of substantially constant envelope. The complex quantized output signal is used in deriving a complex feedback signal within the integrator loop of the complex DSM. The complex quantized output signal may be used in driving a power amplifier substantially at saturation. In some embodiments, an adjacent channel power ratio (ACPR) enhancement technique is used to reduce the quantization noise in the complex quantized output signal.
HYBRID FRACTIONAL PHASE-LOCKED LOOP
A phase-locked loop circuit including a phase detector having a reference clock input; a charge pump having an input coupled to an output of the phase detector; a non-integrating loop filter having an input coupled to an output of the charge pump; a voltage adder having a first input coupled to an output of the loop filter, a voltage-controlled oscillator (VCO) having an input coupled to an output of the voltage adder; and a first frequency divider having an input coupled to an output of the VCO, and an output coupled to the second input of the phase detector. The circuit further includes frequency control circuitry that has an input coupled to the output of the VCO, a reference clock input, and an output coupled to a second input of the voltage adder.