A method of redundantly encoding data includes formatting the data into columns and rows, and generating first and second sets of projections of the data using an encoding transform. For each set of projections generated, an encoding parameter of the encoding transform is set to a different value. The first and second sets of projections are stored as the encoded data. A decoding method reads settings including an indication of a number of data fragments. The number of data fragments is compared to a number of projections in a first set of projections of the encoded data in order to determine whether to use a first or a second decoding mode. The encoded data is then decoded according to the selected decoding mode and the result is outputted.

A device and method for receiving communications with dynamic data correction, the method including receiving at a receiving device a data packet from a sending device, the data packet including a header, and a data payload including one or more message blocks and corresponding redundancy blocks; recognizing, via pre-configuration of the receiving device, that there are redundancy blocks to receive along with the one or more message blocks and reading in the message blocks and corresponding redundancy blocks; determining that at least one of the message blocks is defective (e.g., corrupt, missing, etc.); processing one or more of the redundancy blocks to correct the defective message blocks; and optionally sending a response message to the sending device. The method may further include identifying which message blocks are defective and sending a request for, and receiving, redundancy blocks corresponding to the identified defective message blocks.

The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

A transmitting system, receiving system, and a method of processing broadcast signals are disclosed. The method for processing a broadcast signal in a broadcast receiver comprises receiving a DTV signal including a data group, the data group including mobile service data, segmented known data sequences, long known data sequences and transmission parameter data, compensating carrier frequency offset of the DTV signal and channel-equalizing the carrier frequency offset compensated DTV signal using at least one of the long known data sequences and segmented known data sequences in the data group of the DTV signal, wherein the channel-equalizing includes performing a Error Correction (FEC) decoding on data located between the segmented known data sequences, and. estimating Channel Impulse Response (CIR) using the FEC decoded data as known data.

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

A decoding device that includes a decoding determination unit to determine a procedure of recovering and decoding missing packets in consideration of a packet missing pattern in data including a set of media packets and redundant packets generated by a two-dimensional XOR-based FEC encoding method. Further, a decoding unit executes the recovery of the missing packets according to the procedure determined by the decoding determination unit.

A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.

A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.