In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.

Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.

An apparatus for decoding is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to obtain a first codeword comprising one or more information bits and one or more parity bits, obtain a first parameter corresponding to a code rate of the first codeword, and decode the first codeword using a multi-rate decoder to generate a decoded codeword. The multi rate decoder performs a code reconstruction procedure on the first codeword to generate a reconstructed codeword, and decodes the reconstructed codeword. The processor is further configured to output the decoded codeword.

A node receives transmissions associated with a given set of information bits, wherein each of the transmissions use a different polar code and share one or more information bits of the given set of information bits. The node determines, at each of a plurality of polar decoders of the node, soft information for each information bit included in an associated one of the transmissions, wherein each of the plurality of polar decoders is associated with a different transmission of the transmissions. The node provides, from each polar decoder of the plurality to one or more other polar decoders of the plurality, the determined soft information for any information bits shared by their respective associated transmissions, and uses the provided soft information in an iterative decoding process to decode one or more of the received transmissions.

A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller. Each of first storage regions of each of the nonvolatile memory includes a plurality of second storage regions. Each of pieces of first data includes pieces of second data as storage target data. Third data includes pieces of the second data that are selected one by one from each of the pieces of first data. The memory controller executes first decoding of decoding each of the pieces of first data on the basis of a first error correcting code generated by using the first data, and executes second decoding of decoding the third data including a bit of which reliability, which relates to each bit in each of the second storage regions that fail in the first decoding, is less than reliability of other bits on the basis of a second error correcting code.

A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.