Patent classifications
H03M13/2963
SOFT-INPUT SOFT-OUTPUT DECODING OF BLOCK CODES
A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.
Soft output decoding of polar codes
According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.
SOFT DECODING OF RATE-COMPATIBLE POLAR CODES
A node receives transmissions associated with a given set of information bits, wherein each of the transmissions use a different polar code and share one or more information bits of the given set of information bits. The node determines, at each of a plurality of polar decoders of the node, soft information for each information bit included in an associated one of the transmissions, wherein each of the plurality of polar decoders is associated with a different transmission of the transmissions. The node provides, from each polar decoder of the plurality to one or more other polar decoders of the plurality, the determined soft information for any information bits shared by their respective associated transmissions, and uses the provided soft information in an iterative decoding process to decode one or more of the received transmissions.
Error correction circuit, operating method thereof and data storage device including the same
An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.
Turbo product polar coding with hard decision cleaning
An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.
Low-complexity syndrom based decoding apparatus and method thereof
The present disclosure relates to a low-complexity syndrome based decoding apparatus and method and a low-complexity syndrome based decoding apparatus includes: a hard decision unit which performs hard decision on a current input value to output a hard decision vector; a syndrome calculator which performs a syndrome operation on the hard decision vector and determines an error type of the hard decision vector based on the syndrome operation result; and a decoder which selects a predetermined decoding algorithm in accordance with the error type to perform the decoding, and the error type includes at least one of no error, a single error, and a double error.
Dynamic neighbor and bitline assisted correction for NAND flash storage
A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.
Irregular polar code encoding
A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.
Soft decoding of rate-compatible polar codes
A node receives transmissions associated with a given set of information bits, wherein each of the transmissions use a different polar code and share one or more information bits of the given set of information bits. The node determines, at each of a plurality of polar decoders of the node, soft information for each information bit included in an associated one of the transmissions, wherein each of the plurality of polar decoders is associated with a different transmission of the transmissions. The node provides, from each polar decoder of the plurality to one or more other polar decoders of the plurality, the determined soft information for any information bits shared by their respective associated transmissions, and uses the provided soft information in an iterative decoding process to decode one or more of the received transmissions.
Memory system and method of controlling non-volatile memory
According to one embodiment, a memory system includes a first decoder that decodes read information read from a nonvolatile memory that records therein a multidimensional error-correcting code to output hard decision decoding information of each symbol; a second decoder that performs soft decision decoding in units of component codes for the read information using a soft-input value to output soft decision decoding information of each symbol; a soft-decision-decoding information memory that retains the soft decision decoding information of each symbol; and a soft-input-value specifying unit that obtains the soft-input value of each symbol using the read information and the hard decision decoding information or the soft decision decoding information, and the soft-input-value specifying unit obtains an initial value of the soft-input value using the read information and the hard decision decoding information, and outputs an output decode word obtained as a result of the soft decision decoding when the output decode word is determined to be correct.