Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.

An append-only streams capability may be implemented that allows the host (e.g., the file system) to determine an optimal stream size based on the data to be stored in that stream. The storage device may expose to the host one or more characteristics of the available streams on the device, including but not limited to the maximum number of inactive and active streams on the device, the erase block size, the maximum number of erase blocks that can be written in parallel, and an optimal write size of the data. Using this information, the host may determine which particular stream offered by the device is best suited for the data to be stored.

A decoder includes circuitry and a soft decoder. The circuitry is configured to receive channel hard decisions for respective bits of a Generalized Low-Density Parity Check (GLDPC) code word that includes multiple component code words, including first and second component code words having one or more shared bits, to schedule decoding of the GLDPC code word, and following the decoding, to output the decoded GLDPC code word. The soft decoder is configured to receive the channel hard decisions corresponding to the first component code word, to further receive soft reliability measures that were assigned to the shared bits in decoding the second component code word, and to decode the first component code word based on the channel hard decisions and the soft reliability measures.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. The system maintains decoding states. Each decoding state corresponds to a constiuent codeword of a product codeword and to a decoding procecure. For instance, a BCH decoding state indicates whether the decoding of the respective BCH constituent codeword has previously failed. The decoding of the product codeword depends on the various decoding state. For instance, in a BCH decoding iteration, if a BCH decoding state of a constitutent codeword is set to failed, the BCH decoding of that codeword is skipped.

A method for receiving data frames which consists of determining a reference frame by firm decisions on the value of each bit received and then verifying the reference frame according to an integrity check code used for the transmission. The method may include the following steps: calculating, for each bit of said reference frame, a plausibility value that represents the probability of a transmission error; and, in the event of incompatibility with said integrity check code, identifying in said reference frame a non-empty finite set of the most plausibly erroneous bits in accordance with said plausibility values; listing candidate frames each corresponding respectively to one of the possible combinations of numbers of reversals of the identified most plausibly erroneous bits; and verifying the compatibility of the listed candidate frames with said integrity check code.

A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.

An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (.sub.1, . . . , .sub.r1) to a Groebner basis for (.sub.1, . . . , .sub.r), wherein .sub.r is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.

A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets r.sub.m (r.sub.m is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the r.sub.m) symbols of the r.sub.m symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.