H04B2001/045

CLOCK RECOVERY AND CABLE DIAGNOSTICS FOR ETHERNET PHY

A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

APPARATUS AND METHODS FOR BIAS SWITCHING OF POWER AMPLIFIERS

Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal and a bias control circuit that biases the power amplifier. The power amplifier includes an amplification transistor that receives the RF signal at an input, and a first bias network and a second bias network each connected to the input. The bias control circuit includes a first switch, a first reference current source that provides the first reference current to the first bias network through the first switch, a second switch, and a second reference current source that provides the second reference current to the second bias network through the second switch.

DUAL-MODE AVERAGE POWER TRACKING (APT) CONTROLLER
20220311387 · 2022-09-29 ·

A dual-mode average power tracking (APT) controller operates in a first mode to move the control voltage quickly without concern for ripple or ringing. When this coarse adjustment takes the control voltage to within a desired margin of a target, the controller may switch to a second mode, where the APT controller more slowly approaches the target, but has reduced ringing or ripples. The mode is changed by changing resistance and capacitance values in a loop filter within the APT circuit. In a further aspect, a pulse shaper circuit may inject a pulse to force the control voltage to change more rapidly. By switching modes in this fashion, the control voltage may quickly reach a desired target, and then remain in the second mode during a transmission time slot such that the control voltage is clean throughout.

TRANSMITTER OUTPUT SIGNAL POWER MEASUREMENT APPARATUS

Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

FRONT-END CIRCUIT AND ENCODER
20220307866 · 2022-09-29 ·

A preamplifier amplifies signals input to first and second input terminals. A first switching circuit receives first and second input signals and respectively outputs those signals to the first and second input terminals. A switched capacitor circuit samples two signals amplified by the preamplifier. An integration circuit includes a fully differential operational amplifier outputting amplifying differential signals input between third and fourth input terminals between second and first output terminals, and first and second integration capacitors. A second switching circuit switches a connection relationship between the switched capacitor circuit, and the first and second integration capacitors. A third switching circuit switches a connection relationship between the first and second integration capacitors, and third and fourth output terminals. A cycle including sampling and signal integration is performed twice, and the first to third switching circuits switch the connection relationships each time the cycle changes.

Envelope tracking power amplifier apparatus with predistortion
11431297 · 2022-08-30 · ·

An envelope tracking (ET) power amplifier apparatus with predistortion includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET voltage and a tracker circuit configured to generate the ET voltage based on an ET target voltage. The amplifier circuit may introduce phase and amplitude distortions to the signal being amplified. To offset such distortions, exemplary aspects of the present disclosure add an isogain predistortion circuit in an ET integrated circuit (IC) to correct for amplitude distortions and add a phase modulation predistortion circuit to correct for phase distortions.

DC offset compensation in zero-intermediate frequency mode of a receiver

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

WIDEBAND LOW DISTORTION POWER AMPLIFIER
20170222669 · 2017-08-03 · ·

A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the output, leaving no further scope of nonlinearity in the signal chain.

CALIBRATING TRANSMIT ERROR VECTOR MAGNITUDE USING OVER-THE-AIR LOOPBACK
20170223639 · 2017-08-03 ·

Certain aspects relate to methods and apparatus for calibrating transmit error vector magnitude (EVM) using an over-the-air loopback mechanism. An apparatus includes a first radio frequency (RF) module configured to generate first RF signals based on first intermediate frequency (IF) signals and to output the first RF signals via at least a first antenna element, a second RF module configured to process the first RF signals, as obtained via a second antenna element, and to generate second IF signals, and a baseband module configured to determine a transmit performance metric for the first RF module based on the first IF signals and the second IF signals, determine a first transmit power level based on the determined transmit performance metric, and cause the first RF module to output second RF via the first antenna element at the first transmit power level.

DYNAMIC EVENT DETECTION SYSTEM AND METHOD
20170220668 · 2017-08-03 ·

A method for dynamic event detection based on content from a set of social networking systems including receiving content from the set of social networking systems, identifying a plurality of content associated with a geofence, the content that was generated within a predetermined time period, determining feature values from the plurality of content for each of a set of features, determining an event probability for the geofence based on the feature values, and detecting an event within the geofence in response to the event probability exceeding a threshold event probability.