Patent classifications
H04B2001/305
Automatic gain control schemes for low-power personal area network enhanced data rate (EDR) transceivers
Technologies directed to improving power for wireless transceivers are described. One method processes, in a first power mode, a first portion of a data packet, the first portion being modulated with a FSK modulation. The method determines a first gain value for an amplifier and determines that the first data packet has a second portion that is modulated with a PSK modulation. The method determines a receive signal strength indicator (RSSI) value associated with the first portion and determines that the RSSI does not exceed a threshold value corresponding to a throughput requirement. The method switches to a second power mode, the second power mode being higher in power than the first power mode. The method determines, in the second power mode, a second gain value for the amplifier and process the second portion of the first data packet. The second gain value is determined before the processing the second portion.
Signal quality in received wireless signals in the phase domain of shift keying demodulation
Technologies directed to improving signal quality in received wireless signals in the phase domain of shift keying demodulation are described. One method receives digital data, the digital data including a systematic error as a linear function of residual carrier frequency offset and phase noise (PN). The method extracts first phase data from the digital data, determines, in a phase domain, an estimate of the systematic error using historical phase error data of additional digital data received prior to the digital data, and generate second phase data by subtracting the estimate from the first phase data. The method determines a set of symbols from the second phase data and generates a bit sequence of a data packet from the set of symbols.
Dynamic low-power scheme for wireless transceivers
Technologies directed to improving power for wireless transceivers are described. One method receives, in a low power mode, a data packet over a wireless link and determines a RSSI value and a receive signal quality indicator (RSQI) value. The method stores a record with the RSSI and RSQI values in memory. The method determines an average RSSI value and an average RSQI value from historical RSSI and RSQI values, respectively, stored in records. The method categorizes received data in a first channel quality indicator (CQI) category using the average RSSI value and the average RSQI value and configures the wireless device to operate in another power mode, responsive to the data being in the first CQI. The method processes a subsequent data packet while in the other power mode. In some cases, the other power mode is less than a maximum power mode specified by a wireless standard.
RF Transmitter
A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity
DC offset cancelation for wireless communications
Techniques are disclosed relating to DC interference cancelation in received wireless signals. Disclosed techniques may be performed in the digital domain, in conjunction with analog cancelation techniques. In some embodiments, a receiver apparatus operates a local oscillator at a frequency corresponding to a particular pilot symbol in a received wireless signal. In some embodiments the receiver estimates DC interference at the frequency based on the received pilot symbol (this may be facilitated by the fact that the contents of pilot symbols are known, because they are typically used for channel estimation). In some embodiments, the receiver apparatus is configured to cancel the DC interference based on the estimate to determine received data in subsequently received signals at the frequency. Disclosed techniques may allow narrowband receivers to efficiently use more of their allocated frequency bandwidth, rather than wasting bandwidth near the frequency of the local oscillator.
Optical receivers with DC cancellation bias circuit and embedded offset cancellation
In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.
Offset cancellation
Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.
OFFSET CANCELLATION
Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.
Device and method for determining a DC component
A device for determining a DC component in a zero-IF radio receiver comprises an input configured to receive a complex baseband signal; and an analyzer configured to analyze the complex baseband signal to determine a DC component in the complex baseband signal by selecting at least three samples of the complex baseband signal and determining the intersection of at least two perpendicular bisectors of at least two straight lines, each straight line running through a different pair of two of said selected samples, said intersection representing the DC component. Further, a corresponding method, a radar device and a radar method are disclosed.
OPTICAL RECEIVERS WITH DC CANCELLATION BIAS CIRCUIT AND EMBEDDED OFFSET CANCELLATION
In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.