A direct digital radio having a high-speed RF front end in communication with an antenna, and a radio subsystem that can be configured to form a programmable multi-standard transceiver system. The high-speed RF front including RF inputs configured to receive a plurality of radio frequencies (e.g., frequencies between 400 MHz to 7.2 GHz, millimeter wave frequency signals, etc.) and wideband low noise amplifiers provides amplified signals to RF data converters, analog interfaces, digital interfaces, component interfaces, etc. The programmable multi-standard transceiver is operable in frequencies compatible with multiple networks such as private LTE and 5G networks as well as other wireless IoT standards and WiFi in multi-standard network access equipment. The programmable multi-standard transceiver can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

Systems and methods for operating a beamforming circuit are described. A processor can activate a transmitting element among a plurality of transmitting elements of a beamforming circuit. The processor can activate a receiving element among a plurality of receiving elements of a beamforming circuit. The processor can receive a direct current (DC) signal that represents phase and amplitude of the activated transmitting element and the activated receiving element. The processor can adjust a setting of the beamforming circuit to receive additional DC signals that represent phases and amplitudes of the activated transmitting element and the activated receiving element under the adjusted setting. The processor can determine calibration values for the beamforming circuit based on the DC signal and the additional DC signals.

In accordance with an embodiment, a circuit includes a mixer having a signal input port, a local oscillator input port and an output port, a lowpass filter circuit having an input coupled to the output port of the mixer and a terminal configured to be connected to a shunt capacitor, and a difference circuit having a first input coupled to the output port of the mixer, and a second input coupled to an output of the lowpass filter. The output of the difference circuit substantially rejects a DC signal component at the output port of the mixer.

A millimeter wave mobile phone antenna structure including: a plurality of antenna elements, each antenna element having a port; a plurality of signal acquisition units, each having a mixer and an analog-to-digital converter to produce a digital sampled signal of a sub-carrier signal output by each port; and a baseband signal processor, used for multiplying the digital sampled signal of each sub-carrier signal with a real time channel frequency response related weighting function and sum up the products to obtain a total output value of the antenna structure. The difference between the antenna structure of the present invention and the current millimeter-wave antenna structure of mobile phones is that: the present invention uses antenna elements instead of antenna arrays; and the antenna structure of the present invention provides multi-port output signals, rather than a single output digital, to facilitate the adaptability of received signals combining on the baseband end.

An RF multiplexing switching circuit for an RF front end (e.g., for a mobile communications device transmitting/receiving in the RF region) includes a set of RF inputs and a set of RF outputs outputting to RF filters, the RF inputs and outputs connected by signal paths. The switching circuit includes series switches for creating conducting signal paths for transmitting/receiving RF signals between the RF inputs and outputs, and a set of common shared shunt switches (e.g., for M RF inputs and N RF outputs, M+X shunt switches, where X<N) collectively capable (e.g., in conjunction with the series switches) of pulling to ground potential any RF input and output not on the conducting signal path. The RF switching circuit may be implemented as a band select switch (e.g., where the inputs connect to power amplifiers) or an antenna switch (e.g., where the inputs connect to device antennas).

A receiver includes an antenna block configured to transduce impinging electromagnetic signals into electrical signals; a signal conditioning block configured to condition electrical signals received from the antenna block; and a down-converter block configured to down-convert conditioned electrical signals received from the signal conditioning block. The down-converter block comprises a plurality of signal channels. The receiver further includes a plurality of analog-to-digital converters (ADCs) respectively connected to the signal channels of the down-converter block; and a field-programmable gate array (FPGA). The FPGA is configured to program the down-converter block by selecting a set of mixer frequencies and a set of bandwidths designed to remove interference signals in each signal channel. The selections are calculated to mitigate reductions in dynamic range in the ADCs due to interference. The FPGA is further configured to process digital signals received from the ADCs after the down-converter block has removed the interference signals.

An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

The invention discloses a power mixer, radio frequency circuit, device and equipment, and belongs to the technical field of electronics and communication. The power mixer includes a mixer module, which amplifies an analog baseband current signal by a silicon germanium heterojunction bipolar transistor amplifying circuit, and converts a local oscillator voltage signal into a local oscillator current signal by a silicon germanium heterojunction bipolar transistor switching circuit. The silicon germanium heterojunction bipolar transistor switching circuit receives an amplified analog baseband current signal, and mixes the amplified analog baseband current signal and the local oscillator current signal into a radio frequency current signal; and a transformer module, which converts the radio frequency current signal into a radio frequency power signal and then outputs the radio frequency power signal from the power mixer.

A receiver includes an antenna block configured to transduce impinging electromagnetic signals into electrical signals; a signal conditioning block configured to condition electrical signals received from the antenna block; and a down-converter block configured to down-convert conditioned electrical signals received from the signal conditioning block. The down-converter block comprises a plurality of signal channels. The receiver further includes a plurality of analog-to-digital converters (ADCs) respectively connected to the signal channels of the down-converter block; and a field-programmable gate array (FPGA). The FPGA is configured to program the down-converter block by selecting a set of mixer frequencies and a set of bandwidths designed to remove interference signals in each signal channel. The selections are calculated to mitigate reductions in dynamic range in the ADCs due to interference. The FPGA is further configured to process digital signals received from the ADCs after the down-converter block has removed the interference signals.

There is provide a system comprising a plurality of receivers, each receiver comprising a local oscillator configured to generate a local oscillation signal, a primary mixer configured to mix an input signal with a reference signal at a reference frequency to generate a first output signal, a divider configured to divide the reference signal into a second reference signal at a second frequency and a secondary mixer coupled to the primary mixer and configured to mix the first output signal and the second reference signal at the second frequency. In a first mode, the reference signal for a first of a plurality of the receivers is the local oscillation signal from the first receiver and, in a second mode, the reference signal is the local oscillation signal from another of the plurality of receivers.