A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

An operation method of a first communication node in a communication system may comprise generating a codeword by performing coding on a data stream; generating modulation symbols by performing modulation on the codeword; performing DFT on N modulation symbols among the modulation symbols by using a plurality of DFT units; mapping output symbols of each of the plurality of DFT units to a resource; and performing IFFT on the output symbols mapped to the resource by using an IFFT unit.

An operation method of a first communication node in a communication system may comprise generating a codeword by performing coding on a data stream; generating modulation symbols by performing modulation on the codeword; performing DFT on N modulation symbols among the modulation symbols by using a plurality of DFT units; mapping output symbols of each of the plurality of DFT units to a resource; and performing IFFT on the output symbols mapped to the resource by using an IFFT unit.

A method of processing offset carrier modulated, OCM, ranging signals in a radionavigation system including a plurality of satellite-borne transmitters and at least one ground-based receiver includes receiving a first radionavigation signal from at least one of the plurality of satellite-borne transmitters and down-converting and digitizing the first radionavigation signal to derive therefrom a first OCM signal SA, receiving a second signal SB synchronously broadcast with the first OCM signal SA, the second signal SB having the same or substantially the same center frequency as the first OCM signal SA, coherently combining the first OCM signal SA with the second signal SB at the receiver to generate a combined signal SC, generating a combined correlation value YC corresponding to a correlation of the combined signal SC with a local replica of the first OCM signal SC, and deriving ranging information based on the combined correlation value YC.

A method of processing offset carrier modulated, OCM, ranging signals in a radionavigation system including a plurality of satellite-borne transmitters and at least one ground-based receiver includes receiving a first radionavigation signal from at least one of the plurality of satellite-borne transmitters and down-converting and digitizing the first radionavigation signal to derive therefrom a first OCM signal SA, receiving a second signal SB synchronously broadcast with the first OCM signal SA, the second signal SB having the same or substantially the same center frequency as the first OCM signal SA, coherently combining the first OCM signal SA with the second signal SB at the receiver to generate a combined signal SC, generating a combined correlation value YC corresponding to a correlation of the combined signal SC with a local replica of the first OCM signal SC, and deriving ranging information based on the combined correlation value YC.

A testing system includes: a bilinear polarized antenna for receiving and dividing a circularly polarized radio wave associating with a horizontal and a vertical polarization path of an object-to-be-tested into a first and a second high frequency signal; a phase retarder for delaying a phase of the first high frequency signal by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees; a power splitter for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal; and a high frequency signal transceiver for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal and determining states of the horizontal and vertical polarization paths of the object-to-be-tested based on the power. Therefore, the testing system can speed up testing of the object-to-be-tested.

A testing system includes: a bilinear polarized antenna for receiving and dividing a circularly polarized radio wave associating with a horizontal and a vertical polarization path of an object-to-be-tested into a first and a second high frequency signal; a phase retarder for delaying a phase of the first high frequency signal by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees; a power splitter for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal; and a high frequency signal transceiver for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal and determining states of the horizontal and vertical polarization paths of the object-to-be-tested based on the power. Therefore, the testing system can speed up testing of the object-to-be-tested.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.