Efficient and low-latency cueing means for initiating and updating a process of signal detection and separation in a wideband receiver. The method uses an array of IIR filters that feed an inverted state tree. The inverted state tree provides the directions for separating, detecting, and tracking multiple simultaneous signals that are being received. These signals could be either radar or communications signals and are of widely differing frequencies, bandwidths, and other characteristics. The directions are sent by the cueing system to a set of tunable tracking filters and continuously updated so that the set of tracking filters produce noise-reduced, separated signals on their outputs representing the various simultaneous incoming signals.

A method for estimating a time of arrival of a signal transmitted over a wireless channel, includes receiving the signal by a receiving device; correlating the received signal with a filtered code sequence to create a correlation output, identifying in the correlation output, an observation window associated with a main lobe in the correlation output; and processing the observation window to determine a time of arrival of a first path component in the received signal. The filtered code sequence is formed by incorporating a time of arrival matched filter (TOA-MF) inside predetermined shaped code sequence. The TOA-MF is matched to the predetermined shaped code sequence and is based upon a power delay profile of the wireless channel. The computed shaped code sequence is a convolution of a predetermined shaping sequence and a predetermined code sequence.

A method for estimating a time of arrival of a signal transmitted over a wireless channel, includes receiving the signal by a receiving device; correlating the received signal with a filtered code sequence to create a correlation output, identifying in the correlation output, an observation window associated with a main lobe in the correlation output; and processing the observation window to determine a time of arrival of a first path component in the received signal. The filtered code sequence is formed by incorporating a time of arrival matched filter (TOA-MF) inside predetermined shaped code sequence. The TOA-MF is matched to the predetermined shaped code sequence and is based upon a power delay profile of the wireless channel. The computed shaped code sequence is a convolution of a predetermined shaping sequence and a predetermined code sequence.

A configurable acquisition engine for direct sequence (DS) spread spectrum (SS) is provided that is reconfigurable without increasing memory size for several use cases having different time-frequency uncertainties. The acquisition engine utilizes a frequency-domain decimation filter to reduce the number of output frequency points while still utilizing information from all frequency bins.

A configurable acquisition engine for direct sequence (DS) spread spectrum (SS) is provided that is reconfigurable without increasing memory size for several use cases having different time-frequency uncertainties. The acquisition engine utilizes a frequency-domain decimation filter to reduce the number of output frequency points while still utilizing information from all frequency bins.

The present disclosure discloses an M-ary DCSK method based on chaotic shape-forming filtering. The method includes the following steps: at S1, parameters of a communication system are set; at S2, HP information and LP information to be sent in each time slot are prepared; at S3, the information to be sent is modulated; at S4, a chaotic carrier is generated through a chaotic shape-forming filter; at S5, a transmitted signal is prepared; at S6, down-carrier frequency and matched filter is performed to a received signal; at S7, the sampling of a maximum SNR point is performed to an output signal of a matched filter; at S8, the decision of high priority information bits is resumed; and at S9, the decision of low priority information bits is resumed.

The present disclosure discloses an M-ary DCSK method based on chaotic shape-forming filtering. The method includes the following steps: at S1, parameters of a communication system are set; at S2, HP information and LP information to be sent in each time slot are prepared; at S3, the information to be sent is modulated; at S4, a chaotic carrier is generated through a chaotic shape-forming filter; at S5, a transmitted signal is prepared; at S6, down-carrier frequency and matched filter is performed to a received signal; at S7, the sampling of a maximum SNR point is performed to an output signal of a matched filter; at S8, the decision of high priority information bits is resumed; and at S9, the decision of low priority information bits is resumed.

Circuits for continuous-time analog correlators are provided, comprising: a first VCO that receives an input signal and that outputs a first pulse frequency modulated (PFM) output signal; a second VCO that receives a reference signal and that outputs a second PFM output signal; a first phase frequency detector (PFD) that receives the first PFM output signal and the second PFM output signal and that produces a first PFD output signal; a first delay cell that receives the first PFM output signal and that produces a first delayed signal (DS); a second delay cell that receives the second PFM output signal and that produces a second DS; a second PFD that receives the first DS and the second DS and that produces a second PFD output signal; and a capacitor-digital-to-analog converter (capacitor-DAC) that receives the first PFD output signal and the second PFD output signal and that produces a correlator output.

A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern. The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion sends a timeout warning signal to the address checking circuit portion using a handshaking channel therebetween; said address checking circuit portion being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.

A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern. The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion sends a timeout warning signal to the address checking circuit portion using a handshaking channel therebetween; said address checking circuit portion being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.