Patent classifications
H04B3/232
Sampling point adjustment apparatus and method and program
There is provided a sampling point adjustment apparatus including: a frequency conversion unit that converts a first signal and a second signal into a first narrow band signal and a second narrow band signal through frequency conversion; a central position determination unit that determines a central position of a window of the frequency conversion for the second signal based on an estimated value of a sampling interval offset between the first narrow band signal and the second narrow band signal; and a phase control unit that controls a phase of the second narrow band signal based on the estimated value.
QUARTER WAVELENGTH UNIT DELAY AND COMPLEX WEIGHTING COEFFICIENT CONTINUOUS-TIME FILTERS
Various signal processing techniques may benefit from appropriate handling. For example, certain signal processors may benefit from quarter wavelength unit delay and complex weight coefficient continuous-time filters. A method can include splitting an input signal into a plurality of signal paths. The method can also include complex weighting, for each signal path, a respective signal. The method can further include summing outputs of the signal paths. The method can additionally include providing an output comprising the sum of the signal paths. The complex weighting can be configured to independently control gain, phase and delay of the output signal over broadband.
WIRELINE RECEIVER WITH IMPROVED TIMING AND RELATED MARGINS
A wireline receiver with improved timing and related margins, may comprise a data sampler, a first edge sampler, a second edge sampler, a base phase detection circuit, an additional phase detection circuit, a clock circuit and a phase shifting circuit. The data sampler, the first edge sampler and the second edge sampler may, when triggered by a data clock, a first edge clock and a second edge clock respectively, sample and compare a receiver signal to determine whether the receiver signal exceeds a data threshold level, a first threshold level and a second threshold level, and may therefore provide basis for phase detection. According to the phase detection, the clock circuit may provide the first edge clock and the data clock, and the phase shifting circuit may provide the second edge clock by phase shifting.