H04B3/235

High-speed receiver architecture

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Pure delay estimation

A system for estimating delay between a far-end signal and an echo of the far-end signal in a microphone signal, the system comprising: a buffer configured to store a time-series of far-end samples representing the far-end signal; a first delay estimator configured to form a first estimate of the delay in respect of a speech frame representing speech in the microphone signal; a second delay estimator configured to form a second estimate of the delay for the speech frame by operating a first set of one or more filters on far-end samples selected from the buffer in dependence on an operating delay; a second set of one or more filters for operation on far-end samples; and a controller configured to, in response to a determination that the first estimate of the delay for the speech frame differs from the operating delay for a previous frame by at least a predefined length of time, cause the one or more filters of the second set to operate on far-end samples selected from the buffer according to the first estimate of the delay and, if in respect of one or more speech frames a measure of convergence of the second set of filters exceeds a measure of convergence of the first set of filters by at least a first predefined threshold, update the operating delay using the first estimate of the delay.

FULL-DUPLEX CANCELLATION

Facilitating echo cancellation within communication networks is contemplated, such as but not necessarily limited to facilitating echo cancellation within full-duplex (FDX) communication networks. The echo cancellation may optionally be performed with an echo canceller included as part of or otherwise associated with an FDX node used to facilitate interfacing signaling between a digital domain and an analog domain of a FDX or other communication network.

Channel Quality Indicator for Wireline Channel Degradation Detection
20180152326 · 2018-05-31 ·

Systems and techniques relating to channel degradation detection for communication systems are described. A described system includes a processor and an interface to transmit signals and receive signals via a channel that includes a cable. The processor can be configured to perform echo cancellation based on echo tap values to remove portions of the transmitted signals that appear as echoes within the received signals, signal equalization based on equalizer tap values, or both. The processor can be configured to determine a channel quality indicator of the channel based on one or more of the echo tap values, one or more of the equalizer tap values, or both. The processor can be configured to generate a warning indication based on the channel quality indicator indicating a degradation of the cable or the channel.

ADAPTIVE FILTER WITH MANAGEABLE RESOURCE SHARING
20180145725 · 2018-05-24 ·

The present application relates to an adaptive filter using manageable resource sharing and a method of operating the adaptive filter. The adaptive filter comprises a cluster controller configured for allocating each of several computational blocks to one of several clusters and a routing controller for configuring the routing of tapped delay signals by a routing logic to the respective cluster in accordance with an allocation of the tapped delay signals to the clusters. Each of computational blocks is configured for adjusting one filter coefficient, c.sub.i(n), in one cycle of an iterative procedure according to an adaptive convergence algorithm. The number of computational blocks is less than an order of the adaptive filter.

HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

High-speed receiver architecture

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Channel quality indicator for wireline channel degradation detection

Systems and techniques relating to channel degradation detection for communication systems are described. A described system includes an interface to transmit signals and receive signals via a channel that includes a cable; an echo canceller coupled with the interface, the echo canceller to perform echo cancellation based on echo tap values to remove portions of the transmitted signals that appear as echoes within the received signals; an equalizer coupled with the interface, the equalizer to perform signal equalization based on equalizer tap values, the equalizer tap values being determined based on at least a portion of the received signals to adjust an impulse response of the channel and reduce inter-symbol interference within the received signals; and circuitry configured to determine a return loss channel quality indicator of the channel based on the echo tap values, determine an insertion loss channel quality indicator of the channel based on the equalizer tap values, or both.

Ethernet physical layer transceiver with non-linear neural network equalizers
12166595 · 2024-12-10 · ·

A physical layer transceiver for connecting a host device to a wireline channel medium includes a host interface for coupling to the host device, a line interface for coupling to the channel medium, a transmit path operatively coupled to the host interface and the line interface, a receive path operatively coupled to the line interface and the host interface, and adaptive filter circuitry operatively coupled to at least one of the transmit path and the receive path for filtering signals on the at least one of the transmit path and the receive path, the adaptive filter circuitry including a non-linear equalizer. The non-linear equalizer may be a neural network equalizer based on a multi-layer perceptron or a radial-basis function, or may be a linear equalizer with a non-linear activation function. The non-linear equalizer also may have a front-end filter to reduce input complexity.

TECHNIQUES FOR POWER EFFICIENT AND SMART ECHO CANCELLATION
20240405799 · 2024-12-05 ·

The disclosure relates to techniques for power efficient and smart echo cancellation. An apparatus is provided that comprises a finite impulse response filter having a set of M+1 filter coefficients for filtering values of a reference signal to obtain a first filtered reference signal. The apparatus comprises an interval selector for selecting values of the reference signal associated with a k-th time interval of an echo impulse response having N time intervals. The apparatus comprises M delay elements arranged after the interval selector for successively delaying the selected values. The apparatus comprises M+1 error estimators. A first error estimator is coupled to an output of the interval selector. Each of the remaining M error estimators is coupled to an output of a respective delay element. The M+1 error estimators are configured to determine the M+1 filter coefficients to minimize deviation between the first filtered reference signal and the received signal.