Disclosed are a method and a receiving device for clock frequency synchronization. The method includes the following. A user datagram protocol (UDP) packet is obtained by a receiving device. A value of the data volume of the UDP packet in the cache and a first value are performed, by the receiving device, an operation to obtain the absolute value of the difference between the value of the data volume and the first value. When the absolute value is greater than the preset threshold, a clock frequency of the crystal oscillator in the receiving device is adjusted to obtain a target clock frequency, where after the clock frequency of the crystal oscillator is adjusted, the absolute value of the difference is less than or equal to the preset threshold. The receiving device maintains clock frequency synchronization between the receiving device and the transmitting device based on the target clock frequency.

In certain aspects, the present disclosure is related to devices, methods, systems and/or computer-readable media for use in an isochronous media network in which media devices connected to a network employ one or more synchronization signal to regulate or facilitate the transmission of media signals through the network. In certain aspects, the present disclosure is also related to devices, methods, systems and/or computer-readable media for use in a larger unified, or substantially unified, isochronous network created from aggregating local isochronous media networks in which media devices connected to a network employ a one or more synchronisation signal distributed from a local master clock to regulate or facilitate the transmission of media signals.

An audio distribution system includes an audio source; and a plurality of audio playback devices in communication with each other and with the audio source. A group of the audio playback devices are arranged to render audio content provided by the audio source in synchrony. One of the audio playback devices within the group is configured as an audio master which distributes audio content from the audio source to the other audio playback devices within the group, and one of the plurality of audio playback devices, other than the audio master, is configured as a clock master, which distributes clock information that the group of audio playback devices synchronizes to.

An audio system, method, and computer program product for synchronizing device clocks. The systems, methods and computer program product can establish a first isochronous data stream between a peripheral device and a first device and establish a second isochronous data stream between the first device and a second device to send data between the first and second device. As the two data streams may rely on two different device clocks, e.g., one clock which defines the timing for the first isochronous data stream and a second clock which defines the timing for the second isochronous data stream, the systems, methods, and computer program disclosed herein are configured to maintain synchronization and/or synchronize the first clock with the second clock to prevent data loss due to clock drift.

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

In one example, a method for low-latency multimedia stream reception and output in a receiving device is described. Data packets may be extracted from a multimedia stream received over a network. The sequence of independently decodable units associated with the multimedia stream may be decoded. Each independently decodable unit may include one or more data packets. The sequence of decoded units may be stored in an output buffer. Further, flow of the decoded units from the output buffer to an output device may be controlled based on one of (a) a latency associated with the decoded units and (b) a rate of reception of the decoded units by the output buffer and a rate at which the output device is operating. The decoded units may be rendered on the output device.

A packet-based video network includes: plural packetized video data nodes; a packet switch configured to switch from one of video packet routes to another of video packet routes; and a video synchronizer configured to synchronize the video frame periods of at least nodes acting as packetized video data sources; wherein: each node acting as a packetized video data source is configured to launch onto the network packetized video data such that, for at least video frame periods adjacent to a switching operation: the node launches onto the network packetized video data required for decoding that frame during a predetermined active video data portion of the video frame period, and the node does not launch onto the network packetized video data required for decoding that frame during a predetermined remaining portion of the video frame period; and the switching operation is implemented during the predetermined remaining portion.

It is presented a method for managing a jitter buffer depth for receiving real-time communication. The method is performed in a receiver and comprises the steps of: determining an adaptive bitrate state of the receiver when a current capacity of a communication channel for receiving the real-time communication is below a maximum bitrate for receiving the real-time communication; and increasing a depth of a jitter buffer for receiving the real-time communication when the adaptive bitrate state is determined.

A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).

An apparatus and method for detecting and analyzing spikes in network jitter and the estimation of a jitter buffer target size is disclosed. Detected spikes may be classified as jump spikes or slope spikes, and a clipped size of detected spikes may be used in the estimation of the jitter buffer target. Network characteristics and conditions may also be used in the estimation of the jitter buffer target size. Samples may be modified during playback adaptation to improve audio quality and maintain low delay of a receive chain.