A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

This is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.

A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

This application discloses a clock synchronization method and apparatus, and related storage medium, and pertains to the field of communications technologies. A network device receives an announce message from a first master clock node and an announce message from a second master clock node; and when an identifier of a first clock source node carried in the announce message of the first master clock node is the same as an identifier of a second clock source node carried in the announce message of the second master clock node, selects a master clock node with a smaller clock deviation from the first master clock node and the second master clock node, and then calibrates a clock of the network device based on time information of the master clock node. The precision of clock synchronization by the network device is improved.

A multi-node, quantum communication network for providing quantum-secure time transfer with Damon attack detection is described. The network includes three or more nodes connected via authenticated communication channels forming a closed loop. By determining differences between the local times at as well as the time durations required for photons to travel between the three or more nodes, the network detects a Damon attack, if present. For example, the network imposes a closed loop condition to detect the Damon attack. The network can also use the local time differences and time durations for photon travel between nodes to synchronize the local clocks at the three or more nodes of the network.

A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.