A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

A method for determining a clock synchronization path, and a device, where the method includes determining a first clock synchronization path from a clock injection node of the first network to the first network element based on a request of the first network element and the clock synchronization topology of the first network. A clock synchronization topology is automatically updated based on clock synchronization capability information of a network element, and a clock synchronization path is determined to reduce costs of deploying a clock synchronization path.

A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.

[Problem] To select an optimal transmission path having a minimum total MTIE value of total MTIE values between a plurality of master apparatuses configured to transmit time information serving as a reference and a specific relay apparatus configured to receive the time information via a plurality of relay apparatuses to achieve time synchronization.

[Solution] A time path selection apparatus 30 selects a transmission path employed for time synchronization, on the basis of a MTIE value evaluated in each of relay apparatuses 13 to 16, between master apparatuses 11 and 12 configured to transmit time information serving as a reference and a relay apparatus 15 or 16 at an edge configured to receive the time information via a relay apparatus 13 or 14 to achieve the time synchronization. The time path selection apparatus 30 includes a time information reception unit 31 configured to receive the MTIE value evaluated in each of the relay apparatuses 13 to 16, and an optimal path derivation unit 33 configured to evaluate, on the basis of the received MTIE value, a total MTIE value for every transmission path in transmission paths between the relay apparatus 15 and the master apparatuses 11 and 12 and to select and derive, as the transmission path employed for the transmission path for time synchronization, a transmission path where the total MTIE value is a minimum (170 ns).

A Reference Time Scale Dissemination System (RTS-DS) is provided that includes a RTS Dissemination Data Provider (RTS-DDP) and a User Terminal. The RTS Dissemination Data Provider is equipped with a radio receiver designed to receive radio signals and to compute a RTS-DDP Computed Time Scale based on received radio signals. The User Terminal (UT) is equipped with a Radio Receiver designed to receive radio signals and to compute a UT Computed Time Scale based on received radio signals, and with a Clock Device designed to be locked to the UT Computed Time Scale and to provide a UT Local Time Scale resultingly locked to the UT Computed Time Scale. The RTS-DPP is designed to receive a Reference Time Scale, and compute, at a RTS-DDP Computed Time, Time Quantities indicative of a difference between the RTS-DDP Computed Time Scale and the received Reference Time Scale, including a Time Scatter indicative of a difference between the RTS-DDP Computed Time and a corresponding Reference Time, and a Time Offset indicative of a mean value, computed over a timespan, of a number of differences between RTS-DDP Computed Times and corresponding Reference Times.

A method for communications is proposed. The method may comprise receiving, by a first network node, a report of clock quality of a second network node from a third network node. A clock of the first network node is selected as a master clock for synchronization in a first timing domain, a clock of the second network node is selected as a is selected as a master clock for synchronization in a second timing domain, and the third network node is attached to at least the first timing domain and the second timing domain. Based at least in part on the received report, it may be determined whether to synchronize the first timing domain to the second timing domain. In response to the determination of synchronizing the first timing domain to the second timing domain, the first network node can obtain timing information of the second network node from the third network node. The method may further comprise tuning the clock of the first network node to synchronize the first timing domain to the second timing domain, based at least in part on the timing information of the second network node.

In various implementations, provided are techniques for distributing network time across a network using multiple grand masters (e.g., master time keepers). These techniques include having multiple grand masters simultaneously providing time to the network. Simultaneous means that all the grand masters are active at the same time, and none are designated as backups. In various implementations, the nodes in the network can simultaneously synchronize to network times provided by more than grand masters so that the nodes can obtain more than one network time. Using these multiple network times, nodes configured as clients can determine one network time. The client devices can then use the single network time in applications that require a time.

Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.