An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.

A switching control module can optimize time division duplexing operations of a distributed antenna system (“DAS”). The switching control module can include a measurement receiver and a processor. The measurement receiver can measure signal powers of downlink signals in a downlink path of the DAS. The processor can determine start times for downlink sub-frames transmitted via the downlink path based on downlink signal powers measured by the measurement receiver exceeding a threshold signal power. The processor can identify a clock setting that controls a timing of switching signals used for switching the DAS between an uplink mode and a downlink mode. The processor can statistically determine a switching time adjustment for the clock setting based on switching time differentials between the clock setting and the start times. The processor can update the clock setting based on the switching time adjustment.

The present disclosure provides message sending methods and devices, and target cell selecting methods and devices. One message sending method includes: sending a first message, which carries at least one of clock information and clock accuracy of a cell, to a User Equipment (UE), where the clock accuracy includes at least one of minimum granularity of clock synchronization, a total number of invalid bits of clock synchronization cell, and indication information which indicates whether to support precise clock synchronization.

Provided are a method for performing port configuration of a 5G system (5GS) for providing a time synchronization service, and a network entity performing the same. A method for performing port configuration may include: when a grandmaster (GM) is determined to be a Time Sensitive Networking (TSN) GM outside the 5GS, performing, by a Network Exposure Function (NEF), port configuration of the 5GS in a Best Master Clock Algorithm (BMCA) scheme; and when the GM is determined to be a 5GS GM inside the 5GS, or the TSN GM outside the 5GS that does not support the BMCA, performing, by the NEF, port configuration of the 5GS in an external port configuration scheme.

Provided herein are systems and methods of determining times of events. A server may receive a message from a client in response to an event. The message may identify a first time corresponding to a generation of the event and a second time corresponding to transmission of the message. The first time and the second time may be determined using a first clock of the client. The server may identify, using a second clock of the server, a third time at which the message is received at the server. The server may determine a fourth time based at least on the first time, the second time, and the third time. The fourth time may identify a time according to the second clock at which the event was generated at the client.

The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

A small cell synchronization system uses multiple synchronization sources to obtain maximum performance and stability by utilizing all of the plurality of synchronization sources in a multiple small cell system having two or more different mobile communication small cells as one system and a control method thereof. The small cell synchronization system includes: an oscillator providing a system clock signal of a predetermined frequency; and a synchronization management module that collectively manages multiple synchronization sources, and determines the ‘synchronized PPS’ according to a result of comparing the ‘synchronized PPS’ with the PPS for each synchronization source using the system clock and provides it to each small cell along with the system clock.

An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.