A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.

A station (STA), when operating as a responding STA (RSTA) for time-synchronization of a plurality of initiating STAs (ISTAs) in a time-synchronized network (TSN), may determine, during a negotiation phase, whether each of the ISTAs that intend to participate in one or more measurement phases are requesting to be polled or are requesting not to be polled. For the ISTAs that are requesting to be polled, the RSTA may perform a polling phase prior to performing each of the one or more measurement phases. For the ISTAs that are requesting not to be polled, the RSTA may refrain from performing a polling phase prior to performing each of the one or more measurement phases. The RSTA can directly trigger the measurement phase for ISTAs that are requesting not to be polled. By grouping ISTAs into polling and non-polling groups, efficiency improvements are achieved.

A method for synchronous processing exchange orders, comprising: creating a first batch of orders by accumulating exchange orders received within a first time period, TP1; creating a second batch of orders by accumulating exchange orders received within a second time period, TP2; and processing the orders from the first batch within the second time period, TP2.

A radio receiver device comprises an analogue-to-digital converter clocked by a first clock signal which receives a radio signal. A digital circuit portion receives a digital signal produced by the analogue-to-digital converter and comprises digital processing units clocked by a second clock derived from the first clock and which produce an output signal at an output sample rate. A counter clocked by the second clock counts samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag synchronised to the first clock. The counter is enabled when the flag is set and sets a trigger flag when the count exceeds a predetermined threshold. A buffer receives the output signal and is enabled when the trigger flag is set.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Systems, methods, and devices are described which implement an internal Precision Time Protocol (PTP) instance on a stacked network device within a larger external PTP instance in the network to which the stacked network device. The internal instance of PTP is local to the stacked network device synchronizes the N devices (“members”) in the stack. Each of the members of the stacked network device may act as a BC in this local virtual instance of PTP. One member, which may be referred to as the commander node or primary member node, may synchronize its clock based on an external GSC or external BC, and then that member may act as a BC for a downstream member, and so on in an iterative manner until all of the members within the stacked network device have synchronized clocks. The individual members may also act as BCs to the external endpoints coupled thereto, providing PTP timestamp messages to those endpoints.

A network TAP includes four serial transceivers on a printed circuit board. Each serial transceiver has a medium-dependent interface and a serial differential interface that includes a differential input and a differential output. A passive tap circuit arrangement is configured to be operative at up to 10 Gbps or a higher data rate and configures the differential output signal from the differential output of the first serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the second and third serial transceivers. It also configures the differential output signal from the differential output of the second serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the first and fourth serial transceivers. In one embodiment according to the present invention, the four serial transceivers are pluggable transceiver modules.