An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Disclosed is a method of determining time in a digital processing system, comprising, in a present cycle of a first digital clock: accessing a reference time counter for a reference digital clock, wherein the reference time counter increments in value by a fixed amount at every cycle of the reference digital clock, the reference digital clock being of a higher accuracy than the first digital clock; accessing a first time counter for the first digital clock, wherein the first time counter increments in value by an updatable increment amount at each cycle of the first digital clock; and comparing at least one part of the reference time counter with at least one corresponding part of the first time counter. Based on the comparing, an adjustment is made to one or more attributes of the first time counter, so that first time counter at least approximates the reference time counter.

Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

An optical transceiver is pluggable to any one of a first apparatus and a second apparatus and includes a clock recovery circuit capable of regenerating a clock signal from an electrical signal, a memory storing a first program including a first transmission rate and a second program including a second transmission rate, and a processor executing a program with a higher priority level in a boot process. The processor sets a transmission rate of a program being executed to a transmission rate set value, and operates the clock recovery circuit. In accordance with an interrupt request, the processor sets, based on regeneration or non-regeneration of the clock signal, the priority level of the first or second program that is being executed to be lower than the priority level of the first or second program that is not being executed, and boots up.

Disclosed is a method of determining time in a digital processing system, comprising, in a present cycle of a first digital clock: accessing a reference time counter for a reference digital clock, wherein the reference time counter increments in value by a fixed amount at every cycle of the reference digital clock, the reference digital clock being of a higher accuracy than the first digital clock; accessing a first time counter for the first digital clock, wherein the first time counter increments in value by an updatable increment amount at each cycle of the first digital clock; and comparing at least one part of the reference time counter with at least one corresponding part of the first time counter. Based on the comparing, an adjustment is made to one or more attributes of the first time counter, so that first time counter at least approximates the reference time counter.

Methods, systems, and apparatus for clock synchronization are provided. In one aspect, a clock synchronization method includes: receiving, by a terminal and from an access network device, information about N clock domains, determining, by the terminal, M clock domains that are associated with the terminal and that are in the N clock domains, and separately performing, by the terminal, clock synchronization with clock sources of the M clock domains based on information about the M clock domains. Information about a clock domain includes first time information and a clock domain number of the clock domain. The first time information includes a time of a clock source of the clock domain when the access network device sends the information about the clock domain. The clock domain number identifies the clock domain. N is an integer greater than 1, and M is an integer greater than 1.