H04L1/0066

Code block segmentation and configuration for concatenated turbo and RS coding

A method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. A number N of inner code blocks needed to transmit the transport block is determined. A number M—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. The transport block may then be segmented and encoded according to the calculated encoding parameters.

TRANSMISSION APPARATUS, RECEPTION APPARATUS, COMMUNICATION METHOD, AND INTEGRATED CIRCUIT

A terminal apparatus includes a coding unit configured to divide a transport block into one or more code blocks and generate coded bit(s) by coding the one or more code blocks; and a transmitter configured to transmit the coded bit(s) by using a channel, wherein multiplex bit(s) are given based on at least coupling of the coded bit(s) generated by coding of the one or more code blocks, the coding unit maps the multiplex bit(s) to a matrix in a first-axis prioritized manner and reads the multiplex bit(s) from the matrix in the first-axis prioritized manner or in a second-axis prioritized manner, and whether the first axis or the second axis is prioritized in a case that the multiplex bit(s) are read from the matrix is given based on at least whether a signal waveform applied to a prescribed channel is an OFDM.

Polar code encoding method and apparatus

A polar code encoding method and apparatus are provided. The method includes: obtaining a basic sequence, where the basic sequence is a sequence obtained by sorting sequence numbers of polarized channels in descending order or ascending order of reliability, and a length of the basic sequence is L.sub.1; determining, based on a maximum encoding length L.sub.2 supported by a receiving device, a quantity M of segments of an information bit sequence whose length is N after encoding, where a quantity of bits in the information bit sequence before the encoding is K; and performing polar code encoding on the M segments based on the basic sequence. According to the polar code encoding method, during polar code construction, an encoding device needs to know only a reliability order of min(N/M, L.sub.1) polarized channels. In this way, storage overheads of a nested sequence can be effectively reduced, and online computing complexity can be reduced.

METHODS AND SYSTEMS FOR NETWORK CODING USING CROSS-PACKET CHECK BLOCKS
20210297180 · 2021-09-23 ·

Methods and systems for physical layer network coding based on two-dimensional (2D) joint coding are described. In some methods, first and second packets are obtained. A set of one or more cross-packet check blocks is generated, where each cross-packet check block is generated based on a set of cross-packet bits including at least one bit from each of the first and second packets. At least one cross-packet check block is transmitted to a first communication node.

DATA ENCODING METHOD, DATA DECODING METHOD, AND RELATED DEVICE
20230403098 · 2023-12-14 · ·

Embodiments provide a data encoding method, a data decoding method, and a related device. The method includes a transmitting end device that determines N data symbols at a same symbol location of N links of service data, where N is an integer greater than 1, and quantities of bits in all data symbols are the same. The transmitting end device performs forward error correction (FEC) encoding on the N data symbols to obtain a codeword, where the codeword includes the N data symbols and M overhead symbols, M is an integer greater than or equal to 1 and less than or equal to N, and a quantity of bits in each data symbol is the same as a quantity of bits in each overhead symbol. The transmitting end device sends the N data symbols through N service channels, and sends the M overhead symbols through M overhead channels.

PARALLEL TURBO DECODING WITH NON-UNIFORM WINDOW SIZES
20210176006 · 2021-06-10 ·

A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

Base station apparatus, terminal apparatus, and communication method

To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version.

Enhanced channel interleaving for optimized data throughput
10972210 · 2021-04-06 · ·

In a transmission scheme wherein multi-slot packet transmissions to a remote station can be terminated by an acknowledgment signal from the remote station, code symbols can be efficiently packed over the multi-slot packet so that the remote station can easily decode the data payload of the multi-slot packet by decoding only a portion of the multi-slot packet. Hence, the remote station can signal for the early termination of the multi-slot packet transmission, which thereby increases the data throughput of the system.

BASE STATION APPARATUS, TERMINAL APPARATUS, AND COMMUNICATION METHOD

To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version.

SYSTEM AND METHOD FOR HYBRID-ARQ
20210126655 · 2021-04-29 · ·

Systems and methods are disclosed for providing H-ARQ transmissions in respect of a set of horizontal code blocks are combined in a code. Retransmissions contain vertical parity check blocks which are determined from verticals from the set of horizontal code blocks. Once all the vertical parity check blocks have been transmitted, a new set may be determined after performing interleaving upon either the content of the horizontal code blocks, in the case of non-systematic horizontal code blocks, or over the content of encoder input bits in the place of systematic horizontal code blocks. The interleaving may be bitwise or bit subset-wise. wise. The retransmissions do not contain any of the original bits. In the decoder, soft decisions are produced, and nothing needs to be discarded; decoding will typically improve with each retransmission.