A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately /2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

The present disclosure relates to phase alignment, in particular to phase alignment circuitry (and parts thereof) for example for use in a multiplexer or other circuitry in which data is transmitted from one stage to another. Consideration is given to phase detection and phase rotation. Such circuitry may be implemented as integrated circuitry, for example on an IC chip.

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

A serial transmitter that outputs one symbol every unit interval (UI) from a data source is presented. The serial transmitter includes a serial output port that outputs one symbol every unit interval (UI) from a data source. The serial transmitter also includes a plurality of driver segments that jointly drive the serial output port. Each driver segment is configured to use one of N phases of a sampling clock to serialize and transmit data from the data source. Different sets of the driver segments are configured to use different phases of the sampling clock for serializing and transmitting data, the sampling clock being a half-rate clock having a period of two UI.

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

The present disclosure relates to phase alignment, in particular to phase alignment circuitry (and parts thereof) for example for use in a multiplexer or other circuitry in which data is transmitted from one stage to another. Consideration is given to phase detection and phase rotation. Such circuitry may be implemented as integrated circuitry, for example on an IC chip.

A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.

Circuits, methods, and apparatus that may reconstruct a data signal in the presence of ground drift and high-frequency signal coupling. An illustrative embodiment of the present invention may reconstruct a received data signal by taking an finite difference of the received data signal, detecting edges of the received data signal by detecting positive and negative peaks of the finite difference of the received signal, and reconstructing the received data signal using the detected edges. Taking a finite difference of the received data signal removes the DC component of the received data signal, as well as the ground drift that may cause the DC component of the received data signal to change over time. Additional filtering may be used to reduce high-frequency signal coupling and power supply inductive coupling.