H04L12/40019

Control device, control method, and non-transitory storage medium storing control program

Provided is a control device comprising a communication management part, a computation part, and a result output part. The communication management part is for managing data communication using cyclic communication conforming to a prescribed communication cycle with respect to a field network. The computation part is for measuring a propagation delay time from received data corresponding to actual measurement data for a propagation delay having been transmitted to the field network, and detecting an operation state of the field network using the propagation delay time measurement result. The result output part is for outputting the result of the detection performed by the computation part.

Communication system

Provided is a communication system capable of performing function addition and design change inexpensively. The communication system includes a plurality of slave devices and a master device communicating with the plurality of slave devices. The control blocks control the slave devices or the master device. The input blocks input the input signals to input ports of the control blocks, respectively. The output blocks include semiconductor relays that are turned on and off according to output signals output from the output ports of the control blocks, respectively. The power supply block supplies power to the control blocks. These blocks are configured on separate substrates. The communication block has a communication I/F circuit. The slave devices or the master device are configured by combining plural types of blocks.

COMMUNICATION SYSTEM
20210258186 · 2021-08-19 ·

A communication system, in which a plurality of nodes communicate with each other according to a communication protocol, which wakes up some of the plurality of nodes when a communication frame containing specific start information occurs on or is transmitted to the communication bus, includes a master node determines, for each of slave nodes, a start condition, which is a condition for transition of a subject node from a sleep state to a normal state. The master node transmits, to the communication bus, the determined start condition tailored for each of the slave nodes for a reception thereof by each of the slave nodes.

MASTER SLAVE COMMUNICATION SYSTEM CAPABLE OF REDUCING MANUFACTURING COST, ELECTRONIC DEVICE, CONTROL METHOD FOR MASTER SLAVE COMMUNICATION SYSTEM, AND CONTROL METHOD FOR ELECTRONIC DEVICE
20210297283 · 2021-09-23 ·

A master slave communication system capable of reducing a manufacturing cost is provided. The mater slave communication system includes a master node and a plurality of slave nodes having the same initial address. A communication between the master node and one slave node among the plurality of slave nodes is established by using the initial address set as an address of the one slave node. The address of the one slave node is changed into another address which has been transmitted from the master node to the one slave node through the established communication and is different from the initial address.

Semiconductor device, communication systems and method for controlling the communication system

A semiconductor device capable of improving the efficiencies of communication systems is provided. The semiconductor device comprises: an open period in which reception of data or transmission is allowed; a clock generation circuit defining a close period in which transmission of data and reception are not allowed; and a TSN controller connected to the clock generation circuit and performing transmission of data or reception, wherein the TSN controller performs semiconductor device or reception at another time than open period.

Bus node address verification

Disclosed is a method for detecting an erroneous bus node address allocation in data bus systems with auto addressing using an addressing current, such as LIN data bus systems with auto addressing. The method comprises performing auto addressing of the n bus nodes, causing an addressing current to be supplied by a bus node, sensing the data bus current by the bus nodes and determining a bus node-specific bus current measurement value, deciding, whether an addressing current flows through the respective bus node, and determining a bus node-specific addressing current presence value, transmitting the bus node-specific bus current measurement value and/or the bus node-specific addressing current presence value from the bus node to the bus master, forming a supply bus node-specific result vector from the received bus node-specific addressing current presence values, and comparing the supply bus node-specific result vector and a supply bus node-specific expectation vector.

SINGLE-COUNTER, MULTI-TRIGGER SYSTEMS AND METHODS IN COMMUNICATION SYSTEMS
20210181788 · 2021-06-17 ·

Single-counter, multi-trigger systems and methods in communication systems consolidate tracking of multiple trigger events into a single counter in place of plural counters. The single counter may track multiple trigger events for a single triggered element. Likewise, the single counter may track trigger events for a plurality of triggered elements. By consolidating tracking of trigger events with reference to a single counter, the size of the circuit may be reduced and power savings may be achieved.

Control and data-transfer system, gateway module, I/O module, and method for process control

Meeting the safety requirements of automation systems in a more flexible manner, the invention provides a control and data transmission system for controlling safety-critical processes comprising a plurality of I/O modules connected via a first communication network to a gateway module. The gateway module is connected to a second communication network hierarchically superior to the first communication network and acts as a gateway between the first and the second communication networks. At least one of the I/O modules comprises a diagnosis unit for generating status data relating to the functional state of an input and/or output and/or of a process device. The gateway module and the I/O modules communicate via the first communication network in a safe manner to transfer status data and input and/or output data. The gateway module performs safety processing of the status data and/or of the input and/or output data.

RELAY DEVICE AND MULTI-SPLIT CONTROL SYSTEM

A relay device and a multi-split control system that achieve reliable communication between an outdoor air conditioning unit and multiple indoor units under the condition that the length of a communication bus is limited. The system expands the communication distance by a cascade path formed by a plurality of relay devices. The cascade path transmits control signals sent by a master control device/a specific slave control device (i.e. a slave control device communicating with the master control device or certain relay device) to corresponding slave control devices one by one, and the corresponding slave control devices transmit the signals to the master control device/specific slave control device according to a response signal fed back by the control signal, where the relay devices may respectively communicate with a source node device and a destination node device on the basis of the master-slave type communication mode.

HIGH PRECISION MULTI-CHIP CLOCK SYNCHRONIZATION
20210152269 · 2021-05-20 ·

A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.