Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

A device and a method for a transmitter/receiver device of a bus system are provided. The device has a measuring unit for measuring a minimum recessive bit time that occurs during an operation of the bus system in a message received by the device from a bus of the bus system, a voltage state of the message having been actively driven by a transmitter/receiver device of one of at least two user stations of the bus system; a calculation unit for calculating a power-on period on the basis of the minimum recessive bit time supplied by the measuring unit, the power-on period being a time period for which an oscillation reduction unit is to be switched on, which is used for reducing oscillations on the bus that occur after a transition between different voltage states of a bus signal transmitted on the bus.

A device of the present invention incorporates a data block, received from a Communication Module (CM) connected via an interface, into a frame of a specific format in which a preamble for data synchronization is placed at a head, and transmits the frame to the bus while taking only a data block formed in compliance with an arbitrary Communication Protocol (CP) from a series of frames of the specific format that are constituted from signals detected from the bus. When transmitting data to the bus, the device inserts a code indicating the arbitrary CP into a head part of the preamble, and when a signal corresponding to the head part of the preamble detected from the bus is identified as the code indicating the arbitrary CP, it takes a frame with the identified code to transfer a data block within the taken frame to the CM through the interface.

A communication control device for a user station for a serial bus system. The communication control device controls a communication of the user station with at least one other user station of the bus system, and generates a transmission signal for transmission onto a bus of the bus system and/or to receive a signal from the bus. The communication control device generates the transmission signal according to a frame in which bits having a predetermined temporal length are provided. The communication control device is designed to shorten, in comparison to some other bit of the bit sequence, at least one bit in the frame that is situated in a bit sequence of at least two bits having the same logical value, and the communication control device is designed to not shorten bits that are not situated in a bit sequence of at least two bits having the same logical value.

Disclosed are a module assembly and a multi-master communication method thereof, and more particularly, a module assembly including a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, in which at least one module requiring the data transmission among the plurality of modules performs first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, at least one module performing the first declaration for the transmission intention performs second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation.

A circuit has a driver circuit with a slew-rate controller, an output stage and a monitoring circuit. The output stage is connected to a first bus line and to a second bus line, and the driver circuit is designed to control the output stage on the basis of a first logic signal in such a manner that a corresponding bus voltage is produced between the first bus line and the second bus line. The slew-rate controller is coupled to the driver circuit and is designed to set a slew rate of the driver circuit on the basis of an input signal. The monitoring circuit is designed to generate the input signal for the slew-rate controller, wherein the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame.

The invention relates to an arrangement and a method performing data exchange between various integrated circuits, IC, (3,4,5,6,7) in an automotive control system wherein the data are exchanged by a bus and has the object to enable ASIL C/D system coverage and to tie various ICs (clocks, regulators, memory interfaces, sensor signal conditioners, power management ICs etc.) This is solved the data are exchanged by a bus being ASIL C/D compliant and forming a common protocol to exchange information among the integrated circuits (3,4,5,6,7). The method is solved by functions implemented within the bus as setting the frequency of operation; arbitrating roles of the integrated circuits as master or slave device; checking integrity of exchanged data; frame repetition; detecting bus stuck-at failure modes; filtering or denouncing failures and warnings from peripheral devices; detecting remote out of specification local clock; and monitoring and predicting system reliability and profiling maintenance events.

An extension of the existing CAN FD data transmission protocol. The extension enables the use of the IPv6 protocol for the CAN bus. The CAN FD protocol is further developed in an incompatible way. One modification measure relates to the lengthening of the Data Field, which is positioned in the transmission frame after an Arbitration Field. An arbitrary number of bytes can be entered in the extended Data Field within a specified upper limit. Since the Data Field is transmitted at a higher bit rate field than the Arbitration Field, the data throughput is increased dramatically.

The present invention discloses a method for managing priority-arbitrated access to a set of one or more computational engines of a physical computing device. The method includes providing a multiplexer module and a network bus in the physical computing device, wherein the multiplexer module is connected to the network bus. The method further includes receiving, by the multiplexer module, a first data processing request from a driver and inferring, by the multiplexer module, a first priority class from the first data processing request according to at least one property of the first data processing request. The method further includes manipulating, by the multiplexer module, a priority according to which the physical computing device handles data associated with the first data processing request in relation to data associated with other data processing requests, wherein the priority is determined by the first priority class.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.