Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

A cable assembly improves the signal integrity of high-speed differential data communicated from a host to a device by removing common-mode noise at the device end of the cable before it can enter the device. The cable includes a differential pair of conductors, a ground conductor, and a common-mode suppressor circuit with differential inputs and outputs. The common-mode suppressor circuit forwards differential signals from its inputs to its outputs, but reduces common-mode voltages. It returns common-mode currents to the host via the ground conductor. The common-mode suppressor circuit may include passive and/or active circuits, and may be implemented as an integrated circuit.

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Systems for power over data line applications with low mode conversion are described. For example, an apparatus may include a magnetic core; a first conductive coil wound in a first winding direction around the magnetic core; a second conductive coil wound in a second winding direction around the magnetic core; a first conductive lead connecting a first end of the first conductive coil to a first pin; a second conductive lead connecting a second end of the first conductive coil to a second pin; a third conductive lead connecting a first end of the second conductive coil to a third pin, wherein lengths of the first conductive lead and the third conductive lead are equal; and a fourth conductive lead connecting a second end of the second conductive coil to a fourth pin, wherein lengths of the second conductive lead and the fourth conductive lead are equal.

A transmitting apparatus includes a first signal outputter configured to output a first signal to a receiving apparatus via a first line; and a communicator connected to a second line that connects a receiving-side ground node and the first signal outputter with an AC connection, the receiving-side ground node being supplied with a ground potential of the receiving apparatus, and the communicator being configured to transmit a second signal from the transmitting apparatus to the receiving apparatus by causing a direct current, a magnitude of which changes based on a logic level of the second signal, to flow in the second line, or to receive the second signal from the receiving apparatus by detecting a magnitude of a direct current flowing in the second line.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

An apparatus for performing baseline wander correction is provided. The apparatus may include: a plurality of filters, a common mode voltage generator, and a compensation circuit. The plurality of filters may filter a set of input signals to generate a set of differential signals, the common mode voltage generator may generate a common mode voltage between the set of differential signals, and the compensation circuit may perform compensation related to baseline wander correction on the set of differential signals. Multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.