An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.

A signal transmission circuit that is connected to a communication unit by a signal wiring and performs signal transmission to/from the communication unit via the signal wiring includes: a direct-current supply unit that outputs a direct current with a variable output voltage, superimposes the direct current on the signal, and supplies the direct current to the communication unit via the signal wiring; a signal reception unit that receives the signal from the communication unit; and a signal processing unit that performs signal processing based on the signal received by the signal reception unit, wherein the signal reception unit has an equalizer function that adjusts a waveform of the signal to compensate for attenuation due to the signal wiring, and the output voltage is controlled based on an equalizer setting value used for control of the equalizer function.

Transmitters and communication systems are disclosed. In one example, a transmitter includes first to third serializers that generate first to third serial signals; a first output section configured to set a voltage of a first output terminal; a first output control circuit configured to control an operation of the first output section on the basis of the first serial signal and the second serial signal; a second output section configured to set a voltage of a second output terminal; a second output control circuit configured to control an operation of the second output section on the basis of the third serial signal and the first serial signal; a third output section configured to set a voltage of a third output terminal; and a third output control circuit configured to control an operation of the third output section on the basis of the second serial signal and the third serial signal.

A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0 V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.

A continuous-time linear equalizer (CTLE) having a common-source amplifier configured to receive an input signal and output an output signal in accordance with a biasing current; a current source controlled by a first bias voltage and configured to output the biasing current; an active load controlled by a second bias voltage and configured to be a load of the common-source amplifier; a common-mode sensing circuit configured to sense a common-mode voltage of the output signal; a current source controller configured to output the first bias voltage in accordance with the common-mode voltage and a reference voltage derived from a supply voltage of the active load and a first reference current; and an active load controller configured to output the second bias voltage in accordance with the supply voltage of the active load and a second reference current.

Embodiments of the present disclosure utilizes the natural properties of RFI noise on a wireline link. Since differential RFI noise in the system has some correlation with the common mode noise on the cable, a replica of RFI noise can be regenerated by an adaptive filter based on information about the common mode noise. The replica RFI is subtracted from the equalizer output prior to the data decision circuitry or slicer. In this method, the system does not require expensive cable, nor does the equalizer suffer additional loss due to an RFI notch filter. Since RFI can be detected and mitigated, this information can also be coupled to safety systems to increase functional safety under high EMI conditions.

A sense amplifier latch (SAL) provides complimentary outputs in a reset phase to feed them directly to the Decision Feedback Equalizer (DFE) taps from SAL soft decision (d1x & d1xb) to improve the performance of DFE first tap 1-UI (one unit-interval) critical timing. The latch generates the complimentary resetting values on differential outputs in reset time. The latch enables in the required time i.e., once evaluation is done it shuts the current sinking path. The latch can extrapolate to rail-to-rail input common mode range of operation.

In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise and avoiding mode conversion. A first CMC and AC coupling capacitors are connected in series between a PHY and a twisted wire pair. A DC power supply is DC coupled to the wires via a series connection of a DMC and either matched inductors or a second CMC. Coupled between the DMC and the inductors/CMC is an RC termination circuit comprising a first capacitor coupled to one leg and a matched second capacitor coupled to the other leg. The two capacitors are connected to the same resistor coupled to ground.

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.