System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

A transmitter, a receiver and a transceiver are provided. The transceiver includes a hybrid transceiving circuit and a common-mode voltage control circuit. The hybrid transceiving circuit includes a digital-to-analog converter (DAC) circuit, a line driver coupled to the DAC circuit, a filtering and/or amplifying circuit coupled to the line driver, and an analog-to-digital converter (ADC) circuit coupled to the filtering and/or amplifying circuit. The common-mode voltage control circuit is electrically connected to a node of the hybrid transceiving circuit and is configured to detect a common-mode voltage of the node and to adjust the common-mode voltage of the node.

The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f.sub.1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f.sub.2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f.sub.1 and the common mode encoding the second high-speed clock frequency f.sub.2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

A data transmission link includes a transmitter superpositioning a data signal and a clock signal to generate a first signal. The transmitter transmits the first signal, through a link, wherein, the clock signal has a frequency equal to or higher than a Nyquist frequency of the data signal.

Data transmission method for a two-wire data bus from a transmitter having ports to a receiver having ports. The method comprises the steps of: detecting a first common-mode voltage swing on the ports and forming a first common-mode signal. Detecting a second common-mode voltage swing on the ports and forming a second common-mode signal. The transmitter sending data via the two-wire data bus. The receiver receiving the data. The voltage difference on the ports being compared with a lower and an upper reception threshold, wherein an output of an apparatus element assumes a first or second level on the basis of this comparison. Raising the differential send level if the absolute value of the first common-mode signal is greater than a first threshold value. Raising the upper reception threshold and/or lowering the lower reception threshold if the absolute value of the second common-mode signal is greater than a second threshold value. The method allows the transmission of a datum from the transmitter to the receiver. On the basis of the result of the comparison of the absolute value of the detected first common-mode signal with a first threshold value, the upper reception threshold is raised and/or the lower reception threshold is lowered whenever this absolute value of the first common-mode signal is greater than this first threshold value.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

This on-vehicle communication apparatus is configured to communicate with another on-vehicle communication apparatus by using one differential signal line, and includes: a high-band communication unit configured to generate a high-band signal including communication information and output the high-band signal to the differential signal line; and a low-band communication unit configured to generate a direct-current signal or a low-band signal and to output the direct-current signal or the low-band signal to the differential signal line.

A transmitter for establishing communication between a device and a differential network bus includes current driving means connected to each of the two conduction lines of the differential network bus, through a first and second conduction paths of the transmitter; at least one unidirectional current regulator for extracting a first current equal to a known ratio of a parasitic current circulating through the first conduction path, with a direction inverse to the driving current through the conduction path connected to one of the lines of the differential bus; means for obtaining, from the first current, a second current with a magnitude equal to the original magnitude of the parasitic current; and means for introducing the second current into the second conduction path connected to the other line of the differential bus.