A PoDL system conducts differential data and DC power over the same wire pair, and various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals. The DMCs may use the same magnetic core, and the CMC may be series CMCs that used the same magnetic core.

Data transmission method (d) for a two-wire data bus (Z) from a transmitter (S) having ports (A1, A2) to a receiver (E) having ports (A3, A4). The method comprises the steps of: detecting a first common-mode voltage swing on the ports (A1, A2) and forming a first common-mode signal (k1). Detecting a second common-mode voltage swing on the ports (A3, A4) and forming a second common-mode signal (k2). The transmitter (S) sending data via the two-wire data bus (Z). The receiver (E) receiving the data. The voltage difference on the ports (A3, A4) being compared with a lower and an upper reception threshold (SW4, SW5), wherein an output (0) of an apparatus element (CMP2) assumes a first or second level on the basis of this comparison. Raising the differential send level if the absolute value of the first common-mode signal (k1) is greater than a first threshold value (SW1). Raising the upper reception threshold (SW5) and/or lowering the lower reception threshold (SW4) if the absolute value of the second common-mode signal (k2) is greater than a second threshold value (SW2). The method allows the transmission of a datum from the transmitter (S) to the receiver (E). On the basis of the result of the comparison of the absolute value of the detected first common-mode signal (k1) with a first threshold value (SW1), the upper reception threshold (SW5) is raised and/or the lower reception threshold (SW4) is lowered whenever this absolute value of the first common-mode signal (k1) is greater than this first threshold value (SW1).

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

A transceiver, TX/RX PHY, arranged for bi-directional data communication of a node with a counterpart node connected to a point-to-point network using differential mode signaling over a single twisted-pair cable is disclosed. The transceiver, TX/RX PHY, includes a common mode choke arranged between of the TX/RX PHY and the single twisted-pair cable and provided for common mode current suppression. Further included is a switching arrangement arranged between the TX/RX PHY, the common mode choke and the single twisted-pair cable and configured to switchably change a polarity of one of the windings of the common mode choke. A detection section is included and coupled via the switching arrangement to the common mode choke and configured to detect a common mode signal on the single twisted-pair cable in response to a transmission of a test signal by the counterpart node.

In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a single phase or multi-phase power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals.

A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits N.sub.P that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.sub.P.

In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise and avoiding mode conversion. A first CMC and AC coupling capacitors are connected in series between a PHY and a twisted wire pair. A DC power supply is DC coupled to the wires via a series connection of a DMC and either matched inductors or a second CMC. Coupled between the DMC and the inductors/CMC is an RC termination circuit comprising a first capacitor coupled to one leg and a matched second capacitor coupled to the other leg. The two capacitors are connected to the same resistor coupled to ground.